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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pekmestzi, K.Z. Caraiscos, C.G. |
| Copyright Year | 1994 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece (Pekmestzi, K.Z.; Caraiscos, C.G.) |
| Abstract | Massive insertion of delay elements in a one-way signal flow-graph of an FIR digital filter, and/or proper transfer of delay elements between edges in a two-way signal flow-graph lead to systolic arrays for the implementation of a serial-parallel multiplier, a bit-parallel multiplier, and an FIR digital filter. All of them are of the merged type and exhibit lower latency than existing ones, without any increase in throughput or circuitry.< |
| Starting Page | 105 |
| Ending Page | 108 |
| File Size | 314117 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780317726 |
| DOI | 10.1109/MELCON.1994.381133 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-04-12 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Digital filters Finite impulse response filter Delay Pipelines Systolic arrays Merging Throughput Circuits Interleaved codes Transfer functions |
| Content Type | Text |
| Resource Type | Article |
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