NDLI: Efficient implementations of quadratic digital filters

Content Provider	IEEE Xplore Digital Library
Author	Hsing-Hsing Chiang Nikias, C. Venetsanopoulos, A.
Copyright Year	1974
Abstract	Efficient implementation structures of quadratic filters are introduced in this paper using systolic arrays, distributed arithmetic, and linear convolutions with multipliers. The implementations are based on matrix decompositions and consist of a set of parallel 1-D FIR filters in cascade with a set of sequential square-in add-out type of operations. The structures are compared using various realistic figures of merit such as data throughput delay, cost that is proportional to chip area, and variance of roundoff errors in the filter output assuming fixed-point arithmetic. For comparison purposes, the direct and Biglieri quadratic structures are included in this study. Evaluating the comparative results, the conclusion drawn is that the matrix decomposition realization of a quadratic filter implemented with systolic arrays seems to be offering the best compromise among the various conflicting figures of merit.
Starting Page	1511
Ending Page	1528
Page Count	18
File Size	1174113
File Format	PDF
ISSN	00963518
Volume Number	34
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-12-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital filters Finite impulse response filter Systolic arrays Matrix decomposition Nonlinear filters Arithmetic Throughput Delay Costs Roundoff errors
Content Type	Text
Resource Type	Article
Subject	Signal Processing

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