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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cyril, R. Begueret, J.B. Devall, Y. Montignac, G. Baudry, A. |
| Copyright Year | 2004 |
| Description | Author affiliation: IXL Lab., Univ. of Bordeaux, France (Cyril, R.; Begueret, J.B.; Devall, Y.) |
| Abstract | This paper presents the digitizer developed for the second phase of the ALMA (Atacama Large Millimeter Array) project. This ASIC is a monolithic A/D converter implemented in a BiCMOS 0.25 /spl mu/m. SiGe process from STMicroelectronics. The main features of the ADC are a 3 bit resolution (8 quantization levels), an input bandwidth from 2 to 4 GHz with 4 GHz sample rate. The design architecture of this digitizer is based on a conventional flash analog to digital converter structure. The comparator outputs are coded by a FDL encoder with a 3-bit Gray code. The measurement results, depicted at the end of this paper, show that the converter is operational for clock rates up to 5.5 GHz. The overall chip dissipates 1.4 W under 2.5 V and the die area is 9 mm/sup 2/. |
| Starting Page | 250 |
| Ending Page | 253 |
| File Size | 1222760 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780387155 |
| DOI | 10.1109/ICECS.2004.1399665 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-12-15 |
| Publisher Place | Israel |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Bandwidth Phased arrays Application specific integrated circuits BiCMOS integrated circuits Silicon germanium Germanium silicon alloys Quantization Analog-digital conversion Reflective binary codes Semiconductor device measurement |
| Content Type | Text |
| Resource Type | Article |
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