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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Vanden Bulcke, M. Gonzalez, M. Vandevelde, B. Winters, C. Beyne, E. Larson, L. Harkness, B.R. Gardner, G. Mohamed, M. Sudbury-Holtschlag, J. Meynen, H. |
| Copyright Year | 2003 |
| Description | Author affiliation: IMEC, Leuven, Belgium (Vanden Bulcke, M.; Gonzalez, M.; Vandevelde, B.; Winters, C.; Beyne, E.) |
| Abstract | Microelectronics devices continue to evolve towards increased functionality, thinner die, increased reliability, and reduced cost, requiring a change in material and process requirements for the next generation of packages (i.e. stacked chip packages and wafer level packages (WLP)). Stress reduction is a key factor for many devices, particularly those that have thinner die and those that are subjected to stresses generated by thermal cycling. Wafer level packaging is an area where low stress and high volume manufacturing are critical for achieving good reliability and low manufacturing cost. Dow Coming and IMEC have been investigating a Silicone Under the Bump (SUB) wafer. level package as a potential route towards increased reliability. Including a SUB design into the device architecture provides a route to dissipate the stresses generated by the thermal expansion mismatch between the silicon die and the printed circuit board. Key to the device build is the application of a silicone pad using a photosensitive silicone or a screen printable silicone. In the design, metal traces from the bonding pads are redistributed to the tops of the silicone pads. Solder balls are placed on the metallized pads to complete the interconnection. The elastomeric nature of the pad dissipates the stresses created by the mismatch in CTE between the chip and the PCB and extends device reliability. To build the SUB enabled WLP device it was critical to understand the impact of the new materials on the device process steps. The uniqueness of the material set requires the creation and optimization of plasma cleaning processes specific to silicones, direct-on-silicone metallization and metal etching in the presence of silicones. The application of a solder mask and solder ball placement is required to complete a successful device build. In this paper we will discuss in detail the process steps utilized in building a silicone containing WLP. This will include a discussion on the process challenges including silicone pad integration, metallization, solder mask application and solder ball placement. The methodologies described in this paper can be generally applied for integration of photopatternable silicones into a range of devices and packages. |
| Starting Page | 380 |
| Ending Page | 384 |
| File Size | 369987 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780382056 |
| DOI | 10.1109/EPTC.2003.1271550 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-12-12 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wafer scale integration Packaging Thermal stresses Metallization Manufacturing Microelectronics Materials reliability Cost function Thermal factors Thermal expansion |
| Content Type | Text |
| Resource Type | Article |
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