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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Joly, J. Saint Martin, X. |
| Copyright Year | 1991 |
| Description | Author affiliation: Bull SA, Les Clayes-sous-Bois, France (Joly, J.; Saint Martin, X.) |
| Abstract | Based on their experience in developing and using 16 and 12.5 mils peripheral pitch custom compact single chip packages, the authors analyze the evolution and today's limits of package and board technologies and assembly techniques, with emphasis on manufacturability. The authors present their manufacturing approach and quality and reliability results when using 16 and 12.5 mils peripheral ceramic leaded packages. A detailed analysis of packaging processes and limitations is performed for high pin count ceramic and plastic packages. Competitive packaging methods, pin grid arrays, land grid arrays, and tape automated bonding are compared, and trends for the future are analyzed.< |
| Starting Page | 159 |
| Ending Page | 162 |
| File Size | 472876 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780301552 |
| DOI | 10.1109/IEMT.1991.279768 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-09-16 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Lead Testing Soldering Packaging machines Assembly Manufacturing Ceramics Very large scale integration Silicon Plastic packaging |
| Content Type | Text |
| Resource Type | Article |
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