NDLI: Latest developments in bumping technologies for flip chip and WLCSP packaging

Content Provider	IEEE Xplore Digital Library
Author	Manessis, D. Aschenbrenner, R. Ostmann, A. Reichl, H.
Copyright Year	2008
Description	Author affiliation: Microperipheric Res. Center, Tech. Univ. Berlin, Berlin, Germany (Manessis, D.; Reichl, H.) \|\| Fraunhofer Inst. for Reliability & Microintegration (IZM) Berlin, Berlin, Germany (Aschenbrenner, R.; Ostmann, A.)
Abstract	Stencil printing of solder paste remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. Fraunhofer IZM printing group has developed stencil printing processes to meet the current trends in wafer bumping roadmaps with continuous increase of I/O's and reduced bumping pitch. Mainstream wafer bumping has been performed by using innovative Type 5 (15-25μm) and Type 6 (5-15μm) pastes with both Sn-Pb and Pb-free compositions from 300 μm up to 100 μm pitches for peripheral pad configurations and up to 120 μm for area array configurations. At R&D level, IZM has advanced stencil printing very close to its technological limits at pitches even down to 50 μm. Innovative electroformed and laser-cut with nano-treatment stencils have been manufactured with an extreme thinness of 20 μm for bumping wafers at Ultra fine pitches (UFP) of 100 μm, 80 μm and 60 μm. Specifically, for 100 μm pitch bumping, both type 7 (2-11μm) and type 6 (5-15μm) pastes of eutectic composition Sn63/Pb37 have been successfully employed. Bumping using 25 μm electroformed stencil thickness has yielded bump heights of 42.3±3.8μm and 43.6±3.5μm for type 7 and type 6 pastes, respectively. A newly prototype developed type 8 paste (2-8μm) has been used for the first time to bump chips with peripheral contacts at 80 μm and 60 μm pitch. Bumping at 80 μm pitch with nano-treated laser-cut stencil has yielded bumps of 28 μm in height. For bumping at 60 μm pitch, a 20 μm thick electroformed stencil was used with 35 μmx80 μm oblong apertures. Printing at 60 μm pitch has yielded very promising results and has proved the capability of electroformed technology to manufacture accurate and robust thin stencils. The bump height at 60 μm pitch was measured to be 28 ±3 μm. Paste-in-Resist technology lias been developed as an alternative to stencils in order to overcome the manufacturing difficulties of making extremely small apertures. Paste is printed in resist apertures which have been opened by photolithographic processes. In this way, bumping has been demonstrated up to 50 μm pitches. Complimentary to stencil printing processes, IZM has developed balling technologies up to 400 μm pitch up to 8" wafers with a thickness of 150 μm. Solder balling can be achieved either by "perform ball print" using conventional stencil printers with specially designed stencils or by "ball drop" techniques. Balling technologies have demonstrated the application of 300 μm and 250 μm Sn-Pb and Pb-free balls at respective area array pitches of 500 μm and 400 μm, the main I/O pitches for WL-CSP bumping.
Starting Page	1
Ending Page	6
File Size	2097440
Page Count	6
File Format	PDF
ISBN	9781424433926
ISSN	10898190
e-ISBN	9781424433933
DOI	10.1109/IEMT.2008.5507876
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-04
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Packaging Printing Manufacturing Apertures Tin Costs Optical arrays Research and development Prototypes wafer balling wafer bumping stencil printing ultra fine pitch
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

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Advancements in bumping technologies for flip chip and WLCSP packaging

Characterization of stencil printing parameters for fine pitch wafer bumping

Characterization of stencil printing parameters for fine pitch wafer bumping

Optimization of stencil printing wafer bumping for fine pitch flip chip applications

Technical challenges of stencil printing technology for ultra fine pitch flip

Study of stencil printing technology for fine pitch flip chip bumping

Taguchi design of experiment for wafer bumping by stencil printing

C4NP - data for fine pitch to CSP flip chip solder bumping

Sub-100 micron pitch stencil printing for wafer scale bumping

Latest developments in bumping technologies for flip chip and WLCSP packaging

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