NDLI: Low-cost manufacturing strategy for miniature packaging

Content Provider	IEEE Xplore Digital Library
Author	Nguyen, L. Lee, S. Takiar, H.
Copyright Year	1998
Description	Author affiliation: Nat. Semicond. Corp., Santa Clara, CA, USA (Nguyen, L.)
Abstract	The common view is that as packages decrease in size, as with chip scale packages (CSPs), the cost becomes a major impediment to implementation for high volume production. However, cost is only one aspect. In some cases, even though the cost is higher than standard equivalent surface mount packages, CSPs are still used due to the benefits obtained from miniaturization. Furthermore, current market trends show that CSP costs are falling rapidly, at least with the high volume memory products. In the longer term, the adoption of CSPs will match with the ability of the PCB infrastructure to supply cost-effective substrates. This paper discusses a manufacturing approach for CSPs to produce lower overall cost-of-ownership. The strategy centers on an organic substrate-based CSP that simplifies the back end manufacturing flow, from chip attach to wire bonding to molding through testing and singulation. Devices are attached to the strip-like substrate with designs routed out into a matrix format. This design allows the various assembly operations to be performed on existing equipment tailored previously for leadframe-based packages rather than with dedicated (and expensive) tools. Hence, more flexibility can be obtained from the assembly facilities, which are already equipped with standard equipment, boosting at the same time the machines utilization efficiency. The concept has been demonstrated for 8-lead devices and below. It has been extended to 16-, 20-, 24-, 28-, 48-, 64-, and 100-lead devices, with higher pin counts under development.
Starting Page	473
Ending Page	477
File Size	456065
Page Count	5
File Format	PDF
ISBN	0780345231
ISSN	10898190
DOI	10.1109/IEMT.1998.731174
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-21
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Chip scale packaging Assembly Surface impedance Production Pulp manufacturing Wire Bonding Testing Active matrix organic light emitting diodes
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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