NDLI: Testing iterative logic arrays for delay faults with a constant number of patterns

Content Provider	IEEE Xplore Digital Library
Author	Shyue-Kung Lu Mau-Jung Lu
Copyright Year	2002
Description	Author affiliation: Dept. of Electron. Eng., Fu-Jen Catholic Univ., Taipei, Taiwan (Shyue-Kung Lu; Mau-Jung Lu)
Abstract	Iterative logic arrays (ILAs) are widely used in many applications, e.g., general-purpose processors, digital signal processors, and embedded processors. Owing to the advanced VLSI technology, new defect mechanisms exist in the fabricated circuits. In order to ascertain the quality of manufactured products, the traditional single cell fault model is not sufficient. Therefore, more realistic fault models such as sequential fault models and delay fault models should also be targeted. A cell delay fault occurs if and only if an input transition cannot be propagated to the cell's output through a path in the cell in a specified clock period. It has been shown that all SIC (single input change) pairs of a circuit are sufficient to detect all robustly detectable path delay faults within the circuit. We extend the concept of SIC pairs for iterative logic arrays. We say that an ILA is C-testable for cell delay faults if it is possible to apply all SIC (single input change) pairs to every cell of the array in such a way that the number of test pairs for the array is a constant. Necessary conditions for sending this test set to each cell in the array and propagating faulty effects to the primary outputs are derived. An efficient algorithm is also presented to obtain such a test sequence. We use the pipelined array multiplier as an example to illustrate our approach. The number of test pairs for completely testing of the array is only 80. Moreover, the hardware overhead to make it delay fault testable is about 6%.
Sponsorship	Nat. Sci. Council Ministr. Educ
Starting Page	492
Ending Page	498
File Size	450611
Page Count	7
File Format	PDF
ISBN	078037682X
DOI	10.1109/EMAP.2002.1188889
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-12-04
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Logic arrays Delay Circuit faults Silicon carbide Circuit testing Electrical fault detection Fault detection Digital signal processors Very large scale integration
Content Type	Text
Resource Type	Article

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