NDLI: Scaling feasibility study of planar thin floating gate (FG) NAND Flash devices and size effect challenges beyond 20nm

Content Provider	IEEE Xplore Digital Library
Author	Hang-Ting Lue Yi-Hsuan Hsiao Kuang-Yeu Hsieh Szu-Yu Wang Tahone Yang Kuang-Chao Chen Chih-Yuan Lu
Copyright Year	2011
Description	Author affiliation: Macronix International Co. Ltd, Emerging Central Lab., Technology Development Center, 16, Li-Hsin Road, Hsinchu Science Park, Taiwan (Hang-Ting Lue; Yi-Hsuan Hsiao; Kuang-Yeu Hsieh; Szu-Yu Wang; Tahone Yang; Kuang-Chao Chen; Chih-Yuan Lu)
Abstract	Scaling of the planar thin FG NAND device down to 20nm is experimentally studied for the first time. Using a thin FG (<10nm) and a barrier engineered CT IPD the 20nm device showed reasonable memory window and endurance, but the overall memory window is significantly degraded compared to longer channel devices. Through detailed 3D TCAD simulations we find that the edge fringing field plays the dominant role in the memory window degradation. The conventional short-channel Vt roll-off effect also induces a significant programmed-state subthreshold slope (S.S.) degradation that also reduces the memory window. Control gate height and several device parameters are discussed in order to provide an overview of size effect on the scaling of planar thin FG NAND devices.
File Size	836104
File Format	PDF
ISBN	9781457705069
ISSN	2156017X
e-ISBN	9781457705052
e-ISBN	9781457705045
DOI	10.1109/IEDM.2011.6131519
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programming Degradation Logic gates Tunneling High K dielectric materials Electron traps
Content Type	Text
Resource Type	Article

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