NDLI: Deep submicron nitrided-oxide CMOS technology for 3.3-V operation

Content Provider	IEEE Xplore Digital Library
Author	Hori, T.
Copyright Year	1990
Description	Author affiliation: Matsushita Elect. Ind. Co. Ltd., Osaka, Japan (Hori, T.)
Abstract	Deep-submicron CMOSFETs with ONO (reoxidized nitrided oxide) gate dielectrics have been demonstrated to satisfy 3.3-V operation, contrary to conventional SiO/sub 2/ FETs. The 1.4- mu m ONO CMOS devices achieve (1) an improved saturation transconductance g/sub m/ of 250 mu S/ mu m for n-FETs together with acceptably small degradation in p-FET g/sub m/, resulting in an excellent CMOS gate delay time of 55 ps/stage (comparable or superior to the device/circuit performance of SiO/sub 2/ FETs) and (2) device lifetimes improved by approximately 100 times to exceed 10 years with respect to both ON- and OFF-state hot-carried reliability for n-FETs as well as TDDB together with unchanged p-FET hot-carrier reliability, all under 3.3-V operation.<>
Starting Page	837
Ending Page	840
File Size	342412
Page Count	4
File Format	PDF
ISSN	01631918
DOI	10.1109/IEDM.1990.237032
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology FETs CMOSFETs Dielectrics Transconductance Degradation Delay effects Circuit optimization Hot carriers
Content Type	Text
Resource Type	Article
Subject	Materials Chemistry Electronic, Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering

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