NDLI: High density dual-active-device-layer (DUAL)-CMOS structure with vertical tungsten plug-in wirings

Content Provider	IEEE Xplore Digital Library
Author	Oyama, K. Kunio, T. Koh, R. Hayashi, Y. Kajiyana, K. Tsunenari, K.
Copyright Year	1990
Description	Author affiliation: NEC Corp., Kanagawa, Japan (Oyama, K.; Kunio, T.; Koh, R.; Hayashi, Y.; Kajiyana, K.)
Abstract	A dual-active-device-layer (DUAL)-CMOS structure has been developed for achieving high-density LSIs. It consists of NMOSFETs in a lower bulk-Si and PMOSFETs in an upper SOI film. The most important structural feature is that upper PMOSFET electrodes are directly interconnected to lower NMOSFET electrodes using a vertical tungsten plug-in wiring technique. The plug-in wirings allow the device area to be reduced to approximately 50% that of a conventional bulk-Si CMOS. The contact resistance of the plug-in wiring for the upper and lower MOSFETs did not affect the MOSFET characteristics. It was confirmed that the propagation delay time of a 43-stage ring oscillator was about 10% faster than that for a conventional bulk-Si CMOS.<>
Starting Page	59
Ending Page	62
File Size	345141
Page Count	4
File Format	PDF
ISSN	01631918
DOI	10.1109/IEDM.1990.237226
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Wiring Electrodes Tungsten Contact resistance Propagation delay Ring oscillators
Content Type	Text
Resource Type	Article
Subject	Materials Chemistry Electronic, Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering

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