NDLI: High density 5 Volt-only compatible non-volatile RAM cell

Content Provider	IEEE Xplore Digital Library
Author	Guterman, D.C.
Copyright Year	1982
Description	Author affiliation: United Technologies/MOSTEK, Carrollton, Texas (Guterman, D.C.)
Abstract	A high density, non-volatile RAM cell composed of a volatile RAM component, merged with a non-volatile element which "shadows" the RAM component, is described. Unlike earlier low density Shadow RAM approaches, small cell size is achieved here by utilizing a vertically integrated 1T-1C DRAM element merged with a highly compact, vertically integrated, triple-level poly-silicon floating gate structure. Non-volatile operations on the floating gate stack are performed by Fowler-Nordheim electron injection through both a tunnel oxide, and through a first level to third level poly-silicon sidewall which has proven successful in earlier $E^{2}PROMs.$ The non-volatile approach lends itself readily to 5 Volt-only implementation, using on-chip voltage multiplication techniques, by virtue of the miniscule Fowler-Nordheim charging currents needed, combined with a single high voltage STORE implementation scheme using a common third level poly-Si line. Cell operation for the non-volatile BULK STORE and BULK RECALL functions as well as volatile bit operations are described. Also shown is the cell layout, which consumes 1.5 $mil^{2}area,$ based on 3µ design rules, making it readily compatible with 16K NOVRAM density levels.
Starting Page	728
Ending Page	732
File Size	348936
Page Count	5
File Format	PDF
DOI	10.1109/IEDM.1982.190398
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1982-12-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Read-write memory Voltage Tunneling Random access memory EPROM Secondary generated hot electron injection Dielectrics Silicon Electrodes
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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