NDLI: On-die supply-inducecd jitter behavioral modeling

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On-die supply-inducecd jitter behavioral modeling

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On-die supply-inducecd jitter behavioral modeling

Content Provider	IEEE Xplore Digital Library
Author	Xiaoqing Wang Martin, A.
Copyright Year	2013
Description	Author affiliation: Intel Corp., Santa Clara, CA, USA (Xiaoqing Wang) \|\| Intel Corp., Folsom, CA, USA (Martin, A.)
Abstract	This paper describes a simple, yet efficient supply-induced jitter modeling methodology for high-speed I/O circuits. The proposed model uses the average supply noise and a linear factor derived from Spice simulations to estimate the jitter for a circuit block. For circuits with bias voltages, the transfer function of the biasing network is included. The model is implemented in Simulink and closely correlated with Spice simulations. The modeling accuracy is further validated to be within ±15% of the silicon measurement for the period jitter of a ring oscillator. The jitter modeling technique is applied to multiple memory I/O designs and can be extended to other high-speed interface designs and their timing budgeting.
Starting Page	147
Ending Page	150
File Size	315280
Page Count	4
File Format	PDF
ISBN	9781479907052
e-ISBN	9781479907076
DOI	10.1109/EPEPS.2013.6703486
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Jitter Integrated circuit modeling Noise Delays Mathematical model Computational modeling Ring oscillators high-speed integrated circuits timing jitter power supply noise
Content Type	Text
Resource Type	Article

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