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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Weaver, J.A. Horowitz, M.A. |
| Copyright Year | 2007 |
| Description | Author affiliation: Stanford Univ., Stanford (Weaver, J.A.; Horowitz, M.A.) |
| Abstract | Maintaining low supply impedance is a critical task in modern high-performance chip and system design, and this depends on how the current flows on the chip, package, and board power distribution layers. Using a simple inductive pickup loop previously described, we measure the per-pin via currents for a large VLSI chip in operation. Interestingly, the variation in AC current across the package was only 33%. indicating that for this chip current crowding was not an issue. Furthermore, we measured the board bypass capacitance currents as well, and found that the capacitors supplied between 80%n and 120% of the peak transient currents of the pins to which I hey were connected. Since the maximum current is only slightly larger than the current required by the attached pin, the board bypass capacitance primarily affects the pin it is connected to, and does not really bypass the other VDD pins in that region. |
| Starting Page | 7 |
| Ending Page | 10 |
| File Size | 2350619 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424408832 |
| DOI | 10.1109/EPEP.2007.4387109 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-10-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Current measurement Integrated circuit measurements Current supplies Current distribution Integrated circuit packaging Semiconductor device measurement Capacitance Pins Impedance Power distribution |
| Content Type | Text |
| Resource Type | Article |
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