NDLI: Validation of integrated capacitor-via-planes model

Content Provider	IEEE Xplore Digital Library
Author	Yuan-Liang Li Figueroa, D.G. Teong Guan Yew Chee Yee Chung
Copyright Year	1999
Description	Author affiliation: Intel Corp., Chandler, AZ, USA (Yuan-Liang Li)
Abstract	As clock speeds increase into the GHz regime and rise times decrease into the picosecond regime, the interaction between capacitors and the power/ground planes of the package, interposer, or board on which they are mounted becomes vitally important to the performance of a power delivery system. To include the interaction, this paper provides an integrated model for a discrete capacitor mounted on pads over vias connected to power/ground planes with degassing holes. The mutual inductance between capacitor pads, vias, and power/ground planes are completely modeled. Our modeling results show that the mutual inductance drastically changes the total loop inductance as compared to the self inductance of the capacitor. In some cases, it even reduces the total effective loop inductance. To validate the integrated modeling method, a test package is built. A measurement technique is introduced to evaluate the total loop inductance of the test package with various capacitors. The predicted results matched very well with measured data which give a high confidence on this predicting model and demonstrate the importance of modeling the interaction between capacitors, vias, and planes.
Starting Page	121
Ending Page	124
File Size	289556
Page Count	4
File Format	PDF
ISBN	0780355970
DOI	10.1109/EPEP.1999.819207
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Testing Power system modeling Predictive models Electromagnetic interference Clocks Measurement techniques Electronics packaging Inductance measurement Parasitic capacitance
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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