NDLI: First level package design considerations for the IBM's S/390 G5 server

Content Provider	IEEE Xplore Digital Library
Author	Katopis, G. Becker, D. Stoller, H.
Copyright Year	1998
Description	Author affiliation: S/390 Dev. Lab., IBM Corp., Poughkeepsie, NY, USA (Katopis, G.)
Abstract	Summary form only given. The recently announced S/390 G5 server has achieved many "firsts" in the enterprise server market segment. The most prominent achievement is the virtual elimination of the performance gap at the system level between CMOS and bipolar based microprocessor designs. To this end, many new technology elements were introduced to both the semiconductor and package technologies. Specifically, the microprocessor used many innovative circuit design concepts and an advanced CMOS technology (0.18 /spl mu/m nominal effective channel length) to attain a peak operating frequency of 500 MHz in a chilled operating environment. To support this microprocessor performance with sufficient design margin, the first level package had to operate at 300 MHz under the same environmental conditions. This goal was achieved by the introduction of a glass ceramic MCM containing six layers of a polyimide thin film structure that provided an xy signal line plane pair sandwiched between a power and ground plane for the intra chip connections in addition to the redistribution wiring. This combination of a 127/spl times/127 mm glass ceramic MCM with full field thin film wiring was another technology first and its physical and electrical characteristics are presented here.
Starting Page	15
Ending Page	16
File Size	181472
Page Count	2
File Format	PDF
ISBN	0780349652
DOI	10.1109/EPEP.1998.733490
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Microprocessors Semiconductor device packaging Glass Ceramics Transistors Wiring Circuit synthesis Frequency Polyimides
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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