NDLI: Using GPUs to accelerate FPGA wirelength estimate for use with complex search operators

Content Provider	IEEE Xplore Digital Library
Author	Fobel, C. Grewal, G. Stacey, D.
Copyright Year	2011
Description	Author affiliation: University of Guelph, School of Computer Science, Guelph, ON, Canada (Fobel, C.; Grewal, G.; Stacey, D.)
Abstract	As the precise wirelength for a given placement can only be known after routing, accurate and fast to compute wirelength estimates are required for FPGA placement algorithms. Two of the more effective wirelength estimation models are HPWL [1] and Star+ [2]. However, both of these models are expensive to compute requiring O(nm) time, where n is the number of nets and m is the average number of blocks to connect. In this paper, we show that the time to compute HPWL and Star+ can be reduced by as much as 577× and 548×, respectively, by exploiting the computational power available in modern Graphical Processing Units (GPUs). To reduce the runtime required to compute HPWL and Star+ we propose a set of data structures targeted specifically for the GPU architecture. We then investigate five different mappings of these data structures to the GPU to determine which mapping best exploits the heterogeneous memories and thread-level parallelism available on the GPU. Though our results are geared towards FPGA placement, they extend naturally to the less-constrained VLSI placement problem.
Starting Page	001129
Ending Page	001134
File Size	230485
Page Count	6
File Format	PDF
ISBN	9781424497881
ISSN	08407789
e-ISBN	9781424497898
e-ISBN	9781424497874
DOI	10.1109/CCECE.2011.6030638
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-08
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics processing unit Instruction sets Kernel Data structures Benchmark testing Memory management Field programmable gate arrays
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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