NDLI: Analysis of geometric and non-linear programming as optimization algorithms for low power VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Radfar, M. Mozafari, S.P. Shah, K. Singh, J.
Copyright Year	2011
Description	Author affiliation: La Trobe University, Melbourne, VIC 3083, Australia (Radfar, M.; Shah, K.; Singh, J.) \|\| Amirkabir University of Technology, Tehran, Iran (Mozafari, S.P.)
Abstract	In this paper, performance and accuracy of both General Geometric Programming (GGP) and non-linear programming (NLP) algorithms, for optimization of low power VLSI circuits, have been studied and compared. An optimization procedure based on GGP and logical effort method has been proposed and employed for optimization of variety of sequential logic circuits. The results were compared to the NLP algorithm of Sequential Quadratic Programming (SQP). Experiments showed that the GGP algorithm with Logical Effort method exhibits higher precision and acceptable speed compared to NLP algorithms. In fact, GGP is 9 orders of magnitude more accurate but 24× slower than NLP. However, with increasing circuit complexity the GGP does not degrade like NLP. Consequently, for complex circuits GGP is a good substitution for the speed of NLP algorithms and precision of simple LP (Linear Programming) algorithms, like Logical Effort.
Starting Page	000617
Ending Page	000620
File Size	171086
Page Count	4
File Format	PDF
ISBN	9781424497881
ISSN	08407789
e-ISBN	9781424497898
e-ISBN	9781424497874
DOI	10.1109/CCECE.2011.6030525
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-08
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Optimization Very large scale integration Integrated circuit modeling Logic gates Accuracy Programming NLP Low Power Design VLSI GGP Logical Effort
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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