NDLI: On the implementation of weighted fair queuing in high speed networks

Content Provider	IEEE Xplore Digital Library
Author	Lu, J. Robotham, R.
Copyright Year	2004
Description	Author affiliation: Intelligent Switch & Router, Alcatel Canada Inc., Kanata, Ont., Canada (Lu, J.; Robotham, R.)
Abstract	The fluid generalized processor sharing (GPS) algorithm has desirable properties for integrated services networks and many weighted fair queuing (WFQ) algorithms have been proposed to approximate the GPS. The implementation of WFQ algorithms using calendars (i.e. WFQ calendar) has been proved to be a practical way to realize the WFQ scheduler which supports a large number of queues with diverse rate requirements and at the same time maintains all the important properties of the GPS. However, a WFQ calendar will introduce errors due to the granularity of a calendar and the implementation methods and limitations. What the impacts of the errors are and how to design a WFQ calendar to meet the traffic management requirements become very important in the WFQ calendar design. But there have not been any discussion on this topic. In this paper, a WFQ calendar is modelled, and the implementation errors of WFQ calendars are discovered and analyzed. In addition, the impacts of the errors are discussed, and a few ways to reduce the errors are given.
Sponsorship	Cisco Syst. General Elec. Ryerson Univ. AVFX Audio Visual Bell Canada Dofasco Dye & Durham Gennum Corp. IEEE Canada Found. Univ. of Toronto Niagara College of Appl. Arts and Technol
Starting Page	809
Ending Page	813
File Size	367628
Page Count	5
File Format	PDF
ISBN	0780382536
ISSN	08407789
DOI	10.1109/CCECE.2004.1345237
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-02
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Intelligent networks High-speed networks Calendars Global Positioning System Processor scheduling Switches Bandwidth Robots Technological innovation Intserv networks
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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