NDLI: An advanced library format for ASIC design

Content Provider	IEEE Xplore Digital Library
Author	Karunaratne, M. Sagahyroon, A. Weerakkody, A.
Copyright Year	2004
Description	Author affiliation: V-Cube Technol. Corp, Fremont, CA, USA (Karunaratne, M.)
Abstract	The design of an application specific integrated circuit (ASIC) relies on predefined components called cells. ASIC vendors use proprietary formals to describe technology cells and macro modules in conjunction with numerous translators to feed technology library data to electronic design automation (EDA) tools. Multiple formats are used to represent various aspects of the cells in the same technology library, such as behavior for simulation, timing parameters for synthesis, physical data for layout, noise parameters for signal integrity checks, etc. In addition, most of these are highly-tool oriented mere formats, and are not well-designed self-consistent grammars, and are hard to extend for new data models. In this paper we briefly discuss a library grammar that attempts to bridge the growing gap between new design rules and analysis required for high performance and complex design implementation, and accurate comprehensive modeling of library cells. Its modeling capability is equally applicable for large IP blocks and macro cells, thereby making it suitable for SoC designs as well.
Sponsorship	Cisco Syst. General Elec. Ryerson Univ. AVFX Audio Visual Bell Canada Dofasco Dye & Durham Gennum Corp. IEEE Canada Found. Univ. of Toronto Niagara College of Appl. Arts and Technol
Starting Page	1827
Ending Page	1830
File Size	406838
Page Count	4
File Format	PDF
ISBN	0780382536
ISSN	08407789
DOI	10.1109/CCECE.2004.1349773
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-02
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Libraries Application specific integrated circuits Integrated circuit technology Electronic design automation and methodology Feeds Timing Signal synthesis Data models Bridge circuits Performance analysis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An incremental synthesis method for ASIC design

Obsolete integrated circuit replacement methodology using advanced electronic design automation technology

HDL2GDS: a fully automated ASIC digital design flow

Design closure with cell-based synthesis

New advanced library format standard approved

DAC Highlights

System design based on interface specifications

Physical IP for SOI design infrastructure

On the use of VHDL-based behavioral synthesis for telecom ASIC design

An advanced library format for ASIC design

Similar Documents

An incremental synthesis method for ASIC design

Obsolete integrated circuit replacement methodology using advanced electronic design automation technology

HDL2GDS: a fully automated ASIC digital design flow

Design closure with cell-based synthesis

New advanced library format standard approved

DAC Highlights

System design based on interface specifications

Physical IP for SOI design infrastructure

On the use of VHDL-based behavioral synthesis for telecom ASIC design

An advanced library format for ASIC design