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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Salvador, R. Moreno, F. Riesgo, T. Sekanina, L. |
| Copyright Year | 2010 |
| Abstract | The work reported in this paper describes the steps given towards an FPGA-based implementation of evolvable wavelet transforms for image compression in embedded systems. An Evolutionary Algorithm (EA) for the design and optimization of the transform coefficients is tailored for a suitable System on Chip implementation. Several cut downs on the computing requirements have been done to the original algorithm, adapting it for the FPGA implementation. What this paper addresses more specifically is the validation of the algorithm using fixed point arithmetic for the whole optimization process. The results show how high quality transforms are evolved from scratch with limited precision arithmetic. Also, preliminary results of the implementation in an FPGA device are included. |
| Starting Page | 96 |
| Ending Page | 103 |
| File Size | 450917 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424478392 |
| DOI | 10.1109/DSD.2010.96 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-09-01 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wavelet transforms Multiresolution analysis Hardware Field programmable gate arrays Algorithm design and analysis Image coding |
| Content Type | Text |
| Resource Type | Article |
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