NDLI: A Common Operator for FFT and Viterbi Algorithms

Please wait, while we are loading the content...

2015 Euromicro Conference on Digital System Design

2014 17th Euromicro Conference on Digital System Design

2013 Euromicro Conference on Digital System Design

2012 15th Euromicro Conference on Digital System Design

2011 14th Euromicro Conference on Digital System Design

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

Table of Contents

Message from the General Chairs

Message from the Program Chair

Conference Committees

Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications

Visualization of Multi-objective Design Space Exploration for Embedded Systems

Design of Trace-Based Split Array Caches for Embedded Applications

Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors

An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip

Power Distribution in NoCs Through a Fuzzy Based Selection Strategy for Adaptive Routing

NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems

A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks

Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration

Creation of Partial FPGA Configurations at Run-Time

A Modular Peripheral to Support Self-Reconfiguration in SoCs

High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs

Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications

A Markov Model for Low-Power High-Fidelity Design-Space Exploration

A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder

On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels

QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration

A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints

A Latency-Efficient Router Architecture for CMP Systems

Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies

Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms

Evaluating OpenMP Support Costs on MPSoCs

Re-NUCA: Boosting CMP Performance Through Block Replication

Filtering Directory Lookups in CMPs

Low Latency Recovery from Transient Faults for Pipelined Processor Architectures

RobuCheck: A Robustness Checker for Digital Circuits

Dynamic Control Flow Checking Technique for Reliable Microprocessors

Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations

Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration

Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile

An Improved Automotive Multiple Target Tracking System Design

Medical Diagnosis Improvement Through Image Quality Enhancement Based on Super-Resolution

Generated Cycle-Accurate Profiler for C Language

Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications

Simulation of High-Performance Memory Allocators

Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures

Exploration of Network Alternatives for Middleware-centric Embedded System Design

Adaptive Beamforming Using the Reconfigurable MONTIUM TP

A Common Operator for FFT and Viterbi Algorithms

ALOE-Based Flexible LDPC Decoder

Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA

Adaptive Cache Memories for SMT Processors

Multi-core Technology -- Next Evolution Step in Safety Critical Systems for Industrial Applications?

A Case for Hardware Task Management Support for the StarSS Programming Model

On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms

Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration

System Level Hardening by Computing with Matrices

Faults Coverage Improvement Based on Fault Simulation and Partial Duplication

A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism

A Programming Model and a NoC-Based Architecture for Streaming Applications

Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability

Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application

Area-Efficient Multi-moduli Squarers for RNS

A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications

Low Power FPGA Implementations of 256-bit Luffa Hash Function

On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions

Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m)

An Improved Hardware Implementation of the Grain Stream Cipher

Description-Level Optimisation of Synthesisable Asynchronous Circuits

A Parallel for Loop Memory Template for a High Level Synthesis Compiler

In-channel Flow Control Scheme for Network-on-Chip

An Efficient Method to Reliable Data Transmission in Network-on-Chips

Network-on-Multi-Chip (NoMC) for Multi-FPGA Multimedia Systems

Persistence Management Model for Dynamically Reconfigurable Hardware

System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes

A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol: Implementation and Experimental Validation over a Real-Time Operating system

Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments

Path-Delay Fault Testing in Embedded Content Addressable Memories

Application Dependent FPGA Testing Method

On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism

Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption

A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour

A Design Process for Hardware/Software System Co-design and its Application to Designing a Reconfigurable FPGA

Optimising Self-Timed FPGA Circuits

A New High-Level Methodology for Programming FPGA-Based Smart Camera

Power Consumption Modeling for DVFS Exploitation

Automated Power Characterization for Run-Time Power Emulation of SoC Designs

Customizable Composition and Parameterization of Hardware Design Transformations

Architectural Vulnerability Factor Estimation with Backwards Analysis

Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit

Evaluation of RTD-CMOS Logic Gates

On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications

A Formal Condition to Stop an Incremental Automatic Functional Diagnosis

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

Multiple Bit Error Detection and Correction in Memory

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits

Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor

A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping

Static Average Case Power Estimation Technique for Block Ciphers

An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits

Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis

C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell

Storage-Aware Value Prediction

Computation Reduction Techniques for Vector Median Filtering and their Hardware Implementation

A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder

A Packet Classifier Using a Parallel Branching Program Machine

A Computation and Power Reduction Technique for H.264 Intra Prediction

Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance

An FPGA-Based Accelerator for Analog VLSI Artificial Neural Network Emulation

A Multicore Embedded Processor for Fingerprint Recognition

H.264 Color Components Video Decoding Parallelization on Multi-core Processors

New Digital Control Technique for Improving Transient Response in DC–DC Converters

A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits

A Multicore SDR Architecture for Reconfigurable WiMAX Downlink

Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG

Gracefully Degrading Circuit Controllers Based on Polytronics

LEON3 ViP: A Virtual Platform with Fault Injection Capabilities

Reconfigurable Fault-Tolerant System Sychronization

Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

9th EUROMICRO Conference on Digital System Design (DSD'06)

8th Euromicro Conference on Digital System Design (DSD'05)

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

Euromicro Symposium on Digital System Design, 2003. Proceedings.

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

Proceedings Euromicro Symposium on Digital Systems Design

A Common Operator for FFT and Viterbi Algorithms

Content Provider	IEEE Xplore Digital Library
Author	Naoues, M. Alaus, L. Noguet, D.
Copyright Year	2010
Abstract	In the Software Radio context, the parametrization is becoming an important topic especially when it comes to multi-standard designs. This paper capitalizes on the Common Operator technique to present a new common structure for the FFT and Viterbi algorithms. A key benefit of exhibiting common operators is the regular architecture it brings when implemented in a Common Operator Bank (COB). This regularity makes the architecture open to future function mapping and adapted to accommodated silicon technology variability through dependable design. Global complexity impact is discussed in the paper.
Starting Page	309
Ending Page	313
File Size	579713
Page Count	5
File Format	PDF
ISBN	9781424478392
DOI	10.1109/DSD.2010.80
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-01
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Viterbi algorithm Measurement Software radio Computer architecture Decoding Complexity theory Equations Reconfigurable Radio Parametrization Common Operator FFT Viterbi Butterfly Software Radio
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in