NDLI: Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*

Content Provider	IEEE Xplore Digital Library
Author	Izosimov, V. Pop, P. Eles, P. Peng, Z.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. & Inf. Sci., Linkoping Univ. (Izosimov, V.; Pop, P.; Eles, P.; Peng, Z.)
Abstract	In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safety-critical applications. Processes and messages are statically scheduled. Process re-execution is used for recovering from multiple transient faults. We call process recovery transparent if it does not affect operation of other processes. Transparent recovery has the advantage of fault containment, improved debugability and less memory needed to store the fault-tolerant schedules. However, it will introduce additional delays that can lead to violations of the timing constraints of the application. We propose an algorithm for the mapping of fault-tolerant applications with transparency. The algorithm decides a mapping of processes on computation nodes such that the application is schedulable and the transparency properties imposed by the designer are satisfied. The mapping algorithm is driven by a heuristic that is able to estimate the worst-case schedule length and indicate whether a certain mapping alternative is schedulable
Sponsorship	IEEE CPS
Starting Page	313
Ending Page	322
File Size	223287
Page Count	10
File Format	PDF
ISBN	0769526098
DOI	10.1109/DSD.2006.65
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-30
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerant systems Embedded system Fault tolerance Fault detection Application software Design optimization Software architecture Scheduling algorithm Communication channels Kernel
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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