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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kamala, R.V. Sudhakar, M. Srinivas, M.B. |
| Copyright Year | 2006 |
| Description | Author affiliation: Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Andhra Pradesh (Kamala, R.V.; Sudhakar, M.; Srinivas, M.B.) |
| Abstract | In this paper, the authors propose an efficient reconfigurable Montgomery multiplier for Galois prime field GF(n) that employs carry-save addition. The multiplier can operate for any operand length 'k' where 1<klesN. The value of N determines the maximum operand length that the multiplier can support, which is application dependent. The value 'k' can be changed and hence can be configured and programmed. The final result can be obtained in 'k+1' clock cycles of operation after reset. The advantages of the proposed design are high order of flexibility, which allows easy reconfigurability for any operand length and low hardware complexity. The minimal area overhead to achieve reconfigurability is another major advantage. The critical path delay of the design is 6TXOR+TAND+T4:1MUX+T2:1MUX, where TXOR, TAND, T4:1MUX, and T2:1MUX are delays of 2-input XOR, 2-input AND, 4:1 multiplexer and 2:1 multiplexer respectively. To the best of our knowledge this appears to be the only reconfigurable architecture for Montgomery multiplication over Galois prime field. Further, clock and signal gating techniques have been employed for low-power consumption of the multiplier |
| Sponsorship | IEEE CPS |
| Starting Page | 155 |
| Ending Page | 159 |
| File Size | 123114 |
| Page Count | 5 |
| File Format | |
| ISBN | 0769526098 |
| DOI | 10.1109/DSD.2006.23 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-08-30 |
| Publisher Place | Croatia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay Reconfigurable architectures Field programmable gate arrays Very large scale integration Clocks Multiplexing Arithmetic Elliptic curve cryptography Embedded system Information technology |
| Content Type | Text |
| Resource Type | Article |
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