NDLI: Numerically stable compact strong avalanche model for four-layer device simulation

Content Provider	IEEE Xplore Digital Library
Author	Romo, R.Q.
Copyright Year	2008
Description	Author affiliation: Electr. Eng., Solid State Elecronics CINVESTAV-IPN Mexico D. F., Mexico City (Romo, R.Q.)
Abstract	Since strong avalanche is a central phenomenon in four-layer (PNPN) devices such as thyristors and TOVP's, the usual compact model consisting of two transistors (PNP)- (NPN) must include a numerically stable strong avalanche model. To this end, Miller's empirical expression for avalanche multiplication M(Vcb) in bipolar transistors was modified to eliminate its singularity at the collector-base breakdown voltage $(V_{CBO});$ by substituting a hyperbolic function for Miller's equation when the collector-base voltage $(V_{CBO})$ is higher than 0.99999 $V_{CBO}-$ The combined function is such that it converges asymptotically to a large but finite value for Vcb>Vcbo Furthermore, the function and its first derivative were made continuous at 0.99999 $V_{CBO};$ thus ensuring stability under very strong avalanche. The model, as tested with four layer PSpice (PNP)-(NPN) simulations, did not show any instability or nonphysical results. The resulting limited multiplication factors introduced only a 0.2% voltage overshoot error at breakdown. It was also tested satisfactorily within a circuit based quasi-3D device simulator consisting of several thousand (PNP)-(NPN) transistor pairs.
Starting Page	1
Ending Page	4
File Size	493121
Page Count	4
File Format	PDF
ISBN	9781424419562
DOI	10.1109/ICCDCS.2008.4542659
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-28
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Solid modeling Bipolar transistors Equations Breakdown voltage Circuit testing Computational modeling Avalanche breakdown Thyristors Circuit stability
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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