NDLI: Test chip and infrastructure IP solutions to improve the back-end process during all phases from a new technology development to manufacturing

Content Provider	IEEE Xplore Digital Library
Author	Forli, L. Portal, J.M. Nee, D. Borot, B.
Copyright Year	2004
Description	Author affiliation: L2MP-Polytech, UMR CNRS, Marseille, France (Forli, L.; Portal, J.M.)
Abstract	This paper presents a test chip and infrastructure IP (I-IP) solutions to accelerate process development of interconnects on new advanced technology and to improve the back-end-of-line (BEOL) yield on products. The test chip and the I-IP use the same architecture which is described in using a bottom-up approach with emphasis on its scalability. Using this test chip, the specifications of process back-end critical parameters can be quickly and easily analyzed. Using the dedicated infrastructure IP, the defect density tracking as well as the test and diagnosis of process back-end critical parameters can be rapidly and simply performed. To reach this goal, the test flow and its related signature extraction are given. Moreover, each extracted signature is merged in a database which are used to diagnose defected back-end parameters in the I-IP. Thus, the use of the test chip and the I-IP allows us to improve the manufacturing process from the beginning of a new technology development and integration to the end of ramp-up production and product manufacturing.
Starting Page	77
Ending Page	82
File Size	926114
Page Count	6
File Format	PDF
ISBN	0780387775
DOI	10.1109/ICCDCS.2004.1393357
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-03
Publisher Place	Dominican Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Manufacturing processes CMOS technology Failure analysis Production Semiconductor device manufacture Monitoring Portals Life estimation Scalability
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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