NDLI: Design of the analog components for a high sampling rate continuous time /spl Sigma//spl Delta/ modulator in 0.4 /spl mu/m HEMT technology

Content Provider	IEEE Xplore Digital Library
Author	Olmos, A. Miyashita, T. Nihei, M. Charry, E. Watanabe, Y.
Copyright Year	1998
Description	Author affiliation: Escola Politecnica, Sao Paulo Univ., Brazil (Olmos, A.)
Abstract	The design of the key components for a high sampling rate /spl Sigma//spl Delta/ modulator implemented on a 0.4 /spl mu/m InGaP-InGaAs HEMT technology is described. The circuit, a 2nd-order continuous-time /spl Sigma//spl Delta/ modulator, has a fully differential architecture including pairs of highly linear V-I converters, high-speed opamps, high-speed 1-bit DAC units, and a new polarity alternating feedback (PAF) comparator. Working at a sampling rate of 4.9 GHz and a signal bandwidth of 100 MHz, the fabricated modulator exhibits 43 dB signal-to-noise ratio (SNR), equivalent to 7.2 bits resolution. The circuit occupies an active area of 0.9 mm/sup 2/, and dissipates 400 mW from a 3.2 V power supply. Such performance corresponds to the highest sampling rate and lowest power consumption for an oversampled A/D converter in III-V technology known to us.
Starting Page	138
Ending Page	141
File Size	560194
Page Count	4
File Format	PDF
ISBN	0780344340
DOI	10.1109/ICCDCS.1998.705821
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-03-04
Publisher Place	Venezuela
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sampling methods HEMTs Signal resolution Circuit noise Bandwidth Signal to noise ratio Power supplies Analog-digital conversion Digital modulation Power semiconductor switches
Content Type	Text
Resource Type	Article

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