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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lin Yu Sunkook Kim Mohammadi, S. |
| Copyright Year | 2010 |
| Description | Author affiliation: Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907, USA (Lin Yu; Sunkook Kim; Mohammadi, S.) |
| Abstract | DC and intrinsic low frequency noise properties of p-channel depletion-mode single-walled carbon nanotube field effect transistors (SWCNT-FETs) are investigated. To characterize the intrinsic noise properties a thin atomic layer deposited (ALD) HfO2 gate dielectric which also works as a passivation layer is used to isolate SWCNT-FETs from environmental factors. The SWCNT-FET devices (a prototypical device with 1 CNT is shown in Fig. 1) are fabricated on Si substrate with a 300nm SiO2 thermal oxide. Iron catalyst patterns are defined by UV photolithography with a 10µm spacing and subsequent iron deposition and lift-off. Single-walled carbon nanotubes (SWCNTs) are then synthesized by chemical vapor deposition (CVD) of methane on the substrate coated with patterned Iron catalyst. Source and drain contacts separated by 3µm are formed by electron beam deposition of Pd metal. A 20nm high-k HfO2 film is deposited using ASM Micro-chemistry F-120 $ALCVD^{™}$ Reactor at 300°C by using precursor of HfCl4 and H2O. Top Gate metal is defined by UV photolithography followed by the deposition of Cr/Au (10/50nm) with a minimum gate length of 1.5 µm. Cr/Au (20/450nm) metal interconnects are finally deposited on top of the source and drain Pd contacts. Fig. 2 shows transfer characteristics (Id-Vsg) of a SWCNT-FET with 1.5µm gate-length and 3µm source-drain separation measured in the ambient environment when Vsg is swept from −1.5V to 1V and back to −1.5V. Virtually no hysteresis is observed in the IV characteristics of this device. Figure 3 shows Id-Vsd characteristics of the same device with a maximum on current of 14µA and a maximum transconductance of 6µS at a drain bias of Vsd = 1.5V and gate bias of Vsg = −0.75V. A drain resistance (R) of 120kΩ due to schottky barrier at the drain contact was extracted from IV curves. Drain current in the linear region was modeled according to Id = μeffCg(Vsg+Vt)Vsd/ (L+RμeffCg(Vsg+Vt where Cg = 2πε0ε / $cosh^{−1}(1+h/$ r) ∼ 28af / nm presuming a cylindrical tube model is the gate capacitance per unit length per number of CNTs in the device structure, L is the gate length, εr = 15 is the effective dielectric constant of HfO2, r = 0.5∼2nm is the radius of CNT, h = 20nm is the gate oxide thickness and μeff is the effective field-effect mobility of holes in SWCNT channel. In the current saturation regime where Vsd ≥ Vsg+Vt+RId, SWCNT-FET has a semi-ballistic transport with a drain current modeled as Id = $K(Vsg+Vt)^{3/2}(1+λVsd,$ with effective transconductance K = $1.7×10^{−6}$ $[A/V^{1.5}]$ and channel length modulation parameter λ = $0.2V^{−1}$ are estimated from the measured data. Linear and saturation models are also shown in Fig. 3. Note that the drain resistance R does not influence the current in the saturation regime, but limits it to large source-drain voltages and small effective source-gate voltages Vsg + Vt. |
| Starting Page | 111 |
| Ending Page | 112 |
| File Size | 573167 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424465620 |
| ISSN | 15483770 |
| e-ISBN | 9781424465644 |
| e-ISBN | 9781424465637 |
| DOI | 10.1109/DRC.2010.5551865 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-21 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Noise Current measurement Noise measurement Carbon nanotubes Schottky barriers Metals |
| Content Type | Text |
| Resource Type | Article |
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