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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chao, A.K. Kapur, P. Morifuji, E. Saraswat, K.C. Nishi, Y. |
| Copyright Year | 2007 |
| Description | Author affiliation: Stanford Univ., Stanford (Chao, A.K.; Kapur, P.; Morifuji, E.; Saraswat, K.C.; Nishi, Y.) |
| Abstract | We have developed a self-consistent, electro-thermally coupled, total power, (includes dynamic, DP, and static leakage power, SDL) optimization methodology for future transistors. It calculates the best power-delay tradeoff curve, and the corresponding self-consistent, temperature-delay curves for a given transistor from its current-voltage characteristics. The methodology, by serving as a comprehensive comparison standard for different future transistor options, presents a unique and powerful tool for suitable device selection at future nodes, where no SPICE models are available. In addition, in this work, we also use the methodology to provide insight into the (1) optimum transistor design and operational parameters for minimum $P_{tot},$ (2) device-specific hot spot problems, (3) multi-Vt design for different functional blocks, and (4) the efficacy of novel thermal solutions (superior thermal conductivity, sub-ambient cooling). We choose an 18nm gate length (Lg) double gate FET (DGFET) to illustrate the methodology. |
| Starting Page | 79 |
| Ending Page | 80 |
| File Size | 619065 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424411016 |
| ISSN | 15483770 |
| DOI | 10.1109/DRC.2007.4373659 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-06-18 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delay Thermal resistance Thermal conductivity Cooling Temperature Packaging Coupling circuits Optimization methods Chaos Current-voltage characteristics |
| Content Type | Text |
| Resource Type | Article |
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