NDLI: A flat, timing-driven design system for a high-performance CMOS processor chipset

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A flat, timing-driven design system for a high-performance CMOS processor chipset

Content Provider	IEEE Xplore Digital Library
Author	Koehl, J. Baur, U. Ludwig, T. Kick, B. Pflueger, T.
Copyright Year	1998
Description	Author affiliation: IBM Entwicklung GmbH, Boeblingen, Germany (Koehl, J.)
Abstract	We describe the methodology used for the design of the CMOS processor chipset used in the IBM S/390 Parallel Enterprise Server-Generation 3. The majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. The result is a globally optimized solution without artificial floorplan boundaries. We show that the density in terms of transistors per mm/sup 2/ is comparable to the most advanced custom designs and that the impact of interconnect delay on the cycle time is very small. Compared to custom design, this approach offers excellent turn-around-time and considerably reduces overall effort.
Starting Page	312
Ending Page	320
File Size	139687
Page Count	9
File Format	PDF
ISBN	0818683597
DOI	10.1109/DATE.1998.655874
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-02-23
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process Circuit testing Design optimization Timing Logic arrays Algorithm design and analysis Circuit synthesis Virtual manufacturing CMOS logic circuits Transistors
Content Type	Text
Resource Type	Article

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