NDLI: VVDS: A Verification/Diagnosis System for VHDL

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DAC '89 [Cover page]

DAC'89 Title Page

DAC'89 Copyright Page

Executive Committee

General Chair's Message

1989 Program Committee

Call for Papers

Advance Registration Form - 27th Design Automation Conference

Table of contents

The Last Decade of Design Automation. And the next.

Scheduling and Binding Algorithms for High-Level Synthesis

A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs

Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers

A Framework for Scheduling Multi-rate Circuit Simulation

Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator

Template Style Considerations for Sea-of-Gates Layout Generation

Gate Matrix Layout Synthesis with Two-Dimensional Folding

Transistor Size Optimization in the Tailor Layout System

Tutorial/Panel Languages for Behavioral Description and Synthesis

VLSI Design Language Standardization Effort in Japan

Experience with the ADAM Synthesis System

Architectural Partitioning for System Level Design

Integrated Scheduling and Binding : A Synthesis Approach for Design Space Exploration

Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions

Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation

Scheduling High-Level Blocks for Functional Simulation

Massively Parallel Switch-Level Simulation: A Feasibility Study

Data Parallel Simulation Using Time-Warp on the Connection Machine

LASSIE: Structure to Layout for Behavioral Synthesis Tools

Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout

Performance Optimized Floor Planning by Graph Planarization

ORCA A Sea-of-gates Place and Route System

Tutorial/Panel Social Impact of Computerization

The Social Implications of Computerization: Making the Technology Humane

The MICON System for Computer Design

Gabriel: A Design Environment for Programmable DSPs

Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions

On Global Wire Ordering for Macro-Cell Routing

A New Approach to the Rectilinear Steiner Tree Problem

A New Heuristic for Single Row Routing Problems

IRSIM: An Incremental MOS Switch-Level Simulator

Automatic Generation of Behavioral Models from Switch-Level Descriptions

Locating Functional Errors in Logic Circuits

Tutorial/Panel Case for Electronic Design Automation

CASE Environments for Design Automation

An Object Oriented Approach to CAD Tool Control within a Design Framework

DeBuMA: Description, Building and Management of Applications

Experience with the D-BUS Architecture for a Design Automation Framework

Multi-Level Logic Synthesis Using Communication Complexity

Efficient Prime Factorization of Logic Expressions

New Methods in the Analysis of Logic Minimization Data and Algorithms

The Layout Synthesizer: An Automatic Netlist-to-Layout System

GENAC: An Automatic Cell Synthesis Tool

A Module Generator for Optimized CMOS Buffers

Panel: CAD Tool Needs for High Performance Systems

Use of Change Coordination in an Information-Rich Design Environment

Database Support for Evolving Design Objects

Protection and Versioning for OCT

Approaches to Multi-Level Sequential Logic Synthesis

Multi-Level Logic Simplification Using Don't Cares and Filters

Automatic Synthesis of Boolean Equations Using Programmable Array Logic

An Efficient Two-Dimensional Layout Compaction Algorithm

Technology Tracking of Non Manhattan VLSI Layout

Automatic Tub Region Generation for Symbolic Layout Compaction

Tutorial/Panel: Competitive Design Methodologies for ASICs

Three Competing Design Methodologies for ASIC's: Architectural Synthesis, Logic Synthesis and Module Generation

General Decomposition of Sequential Machines: Relationships to State Assignment

State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory

NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations

Horizontal Partitioning of PLA-based Finite State Machines

A Parallel Branch and Bound Algorithm for Test Generation

Test Pattern Generation for Stuck-Open Faults Using Stuck-At Test Sets in CMOS Combinational Circuits

A Deterministic Approach to Adjacency Testing for Delay Faults

Parallel Pattern Fault Simulation of Path Delay Faults

Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement

Performance-Driven Placement of Cell Based IC's

An Analytic Optimization Technique for Placement of Macro-Cells

An Investigation into Statistical Properties of Partitioning and Floorplanning Problems

Tutorial/Panel: Multi-Chip Modules for Hybrid Package

Multi Chip Modules

Automatic Layout of Silicon-On-Silicon Hybrid Packages

Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks

A Neural Network Design for Circuit Partitioning

A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD

Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation

Differential Fault Simulation - A Fast Method Using Minimal Memory

An Automatic Test Generation Algorithm for Hardware Description Languages

VVDS: A Verification/Diagnosis System for VHDL

Verification of Hardware Descriptions by Retargetable Code Generation

GRASP: A Grammar-based Schematic Parser

Design for Manufacturability and Yield

MIOS: A Flexible System for PCB Manufacturing

FACE Core Environment: The Model and its Application in CAE/CAD Tool Development

An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules

Representation and Use of Design Rules within a Technology Adaptable CAD System

Computing Signal Delay in General RC Networks by Tree/Link Partitioning

Worst-Case Delay Estimation of Transistor Groups

Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits

An O(n log m) Algorithm for VLSI Design Rule Checking

The Use of Inverse Layout Trees for Hierarchical Design Rule Checking

Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour

MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits

A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing

A Scheme for Overlaying Concurrent Testing of VLSI Circuits

ACE: A Hierarchical Graphical Interface for Architectural Synthesis

ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software

High-Level Graphical User Interface Management in the FACE Synthesis Environment

On the General False Path Problem in Timing Analysis

Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network

Static Timing Analysis of Dynamically Sensitizable Paths

Average Interconnection Length and Interconnection Distribution Based on Rent's Rule

Efficient Final Placement Based on Nets-as-points

PIAF: A Knowledge-based/Algorithmic Top-down Floorplanning System

Efficient Floorplan Area Optimization

A Parallel Row-Based Algorithm for Standard Cell Placement with Integrated Error Control

A Note on Clustering Modules for Floorplanning

An Interactive Tool for Register-Level Structure Optimization

A Technology-Adaptive Allocation of Functional Units and Connections

VHDL Synthesis Using Structured Modeling

Capturing Designer Expertise The CGEN System

Evaluation of a Reconfigurable Architecture for Digital Beamforming Using the OODRA Workbench

An ASIC Methodology for Mixed Analog-Digital Simulation

FACET - A CAE System for RF Analogue Simulation Including Layout

A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators

iSMILE: A Novel Circuit Simulation Program with emphasis on New Device Model Development

AWEsim: Asymptotic Waveform Evaluation for Timing Analysis

A Novel Approach to Accurate Timing Verification Using RTL Descriptions

Evaluating Hardware Models in DIGITAL's System Simulation Environment

Algorithms for Accuracy Enhancement in a Hardware Logic Simulator

Efficient Algorithms for Extracting the K Most Critical Paths in Timing Analysis

Timing Analysis in a Logic Synthesis Environment

Rule-Based VLSI Verification System Constrained by Layout Parasitics

Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator

Special Purpose Architecture for Accelerating Bitmap DRC

An Efficient Finite Element Method for Submicron IC Capacitance Extraction

Resistance Extraction and Resistance Calculation in GOALIE2

From Network to Artwork

Extracting Schematic-Like Information from CMOS Circuit Net-Lists

REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures

A Comparison of Four Two-Dimensional Gate Matrix Layout Tools

Plowing: Modifying Cells and Routing in 45°-Layouts

CrossCheck: A Cell Based VLSI Testability Solution

On the Repair of Redundant RAMs

CMOS Stuck-Open Fault Detection Using Single Test Patterns

ATLAS/ELA: Scan-Based Software Tools for Reducing System Debug Time in a State-of-the-Art Workstation

A Functional-Level Test Generation Methodology Using Two-Level Representations

A New Approach to Derive Robust Tests for Stuck-Open Faults in CMOS Combinational Logic Circuits

A Simplified Six-Waveform Type Method for Delay Fault Testing

A Massively Parallel Algorithm for Fault Simulation on the Connection Machine

A New Model for the High Level Description and Simulation of VLSI Networks

Toward Synthesis from English Descriptions

Behavioral Modeling of Transmission Gates in VHDL

VCOMP: A VHDL Composition System

Designer Controlled Behavioral Synthesis

Partitioning by Probability Condensation

Fast Hypergraph Partition

An Evolution-Based Approach to Partitioning ASIC Systems

Min-Cost Partitioning on a Tree Structure and Applications

Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms

Compaction of a Routed Channel on the Connection Machine

Automatic Sizing of Power/Ground (P/G) Networks in VLSI

Optimum Design of Reliable IC Power Networks Having General Graph Topologies

DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions

DTR: A Defect-Tolerant Routing Algorithm

Via Minimization by Layout Modification

A Unified Data Exchange Environment Based on EDIF

The Object-Oriented Integration Methodology of the Cadlab Work Station Design Environment

A Unified Design Representation Can Work

An Object-Oriented Datamodel for the VLSI Design System PLAYOUT

CEDIF: A Data Driven EDIF Reader

Fast Online/Offline Netlist Compilation of Hierarchical Schematics

Loop Optimization in Register-Transfer Scheduling for DSP-Systems

Semantics of a Hardware Design Language for Japanese Standardization

25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

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VVDS: A Verification/Diagnosis System for VHDL

Content Provider	IEEE Xplore Digital Library
Author	Heh-Tyan Liaw Kim-Thu Tran Chen-Shang Lin
Copyright Year	1989
Description	Author affiliation: Department of Electrical Engeneering, National Taiwan University, Taipei, Taiwan, ROC (Heh-Tyan Liaw)
Abstract	In this paper, an interactive verification and diagnosis system for VHDL [Vm88], VVDS, is presented. In VVDS, hybrid simulation, which simulates with both numerical and symbolic data, is implemented to achieve an effective compromise of the enormous quantity of input test data in the conventional simulation and the complexity of symbolic expression in the symbolic execution. To support efficient user interface in the verification and diagnosis process, both on-line programming of commands and micro-probing capability to passively and actively probe any level of design hierarchy are provided.
Starting Page	435
Ending Page	440
File Size	778364
Page Count	6
File Format	PDF
ISBN	0897913108
ISSN	0738100X
DOI	10.1109/DAC.1989.203437
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-06-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Testing User interfaces Numerical simulation Probes Chip scale packaging Formal verification Permission Hardware design languages Error correction Very large scale integration
Content Type	Text
Resource Type	Article

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