NDLI: Multi-Level Logic Simplification Using Don't Cares and Filters

Content Provider	IEEE Xplore Digital Library
Author	Saldanha, A. Wang, A.R. Brayton, R.K. Sangiovanni-Vincentelli, A.L.
Copyright Year	1989
Description	Author affiliation: EECS Department, University of Califronia, Berkeley, Berkeley, CA (Saldanha, A.)
Abstract	Simplification of a multi-level network is used to perform form transformations on parts of the network to obtain an alternate structure that is optimal with respect to area. A technique for obtaining such an optimal structure involves the use of two-level logic minimization on the components of the multi-level logic network. At each component, the structure of the network is captured by intermediate and fan-out don't care sets, which are utilized in the two-level minimization. However, the generation of all the don't cares yield very large sets for most networks and consequently the complete minimization of the components of the circuits require a very large amount of computer time. In this paper we describe algorithms to reduce the size of the don't care sets, so that only the portions that will be useful in minimization at each component of the circuit are retained. We develop both an exact filter and a heuristic filter that prove to be very effective for a large set of benchmark examples. Results show that our technique achieves the same quality as that obtained by doing complete minimizations at each component of the circuits but in much shorter time. This new approach to simplification of multi-level networks has been incorporated into the MIS (version 2.1) logic synthesis system.
Starting Page	277
Ending Page	282
File Size	716886
Page Count	6
File Format	PDF
ISBN	0897913108
ISSN	0738100X
DOI	10.1109/DAC.1989.203409
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-06-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Filters Computer networks Logic circuits Circuit testing Minimization methods Circuit synthesis Network synthesis Topology Boolean functions Logic functions
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The use of observability and external don't cares for the simplification of multi-level networks

Don't care minimization of multi-level sequential logic networks

Multi-level logic minimization using implicit don't cares

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares

Multi-level logic simplification using don't cares and filters

Don't cares and multi-valued logic network minimization

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Logic Minimization and Testability of 2SPP-P-Circuits

Observability relations and observability don't cares

Multi-Level Logic Simplification Using Don't Cares and Filters

Similar Documents

The use of observability and external don't cares for the simplification of multi-level networks

Don't care minimization of multi-level sequential logic networks

Multi-level logic minimization using implicit don't cares

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares

Multi-level logic simplification using don't cares and filters

Don't cares and multi-valued logic network minimization

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Logic Minimization and Testability of 2SPP-P-Circuits

Observability relations and observability don't cares

Multi-Level Logic Simplification Using Don't Cares and Filters