NDLI: Adjustable contiguity of run-time task allocation in networked many-core systems

Content Provider	IEEE Xplore Digital Library
Author	Fattah, M. Liljeberg, P. Plosila, J. Tenhunen, H.
Copyright Year	2014
Description	Author affiliation: Dept. of Inf. Technol., Univ. of Turku, Turku, Finland (Fattah, M.; Liljeberg, P.; Plosila, J.; Tenhunen, H.)
Abstract	In this paper, we propose a run-time mapping algorithm, CASqA, for networked many-core systems. In this algorithm, the level of contiguousness of the allocated processors (α) can be adjusted in a fine-grained fashion. A strictly contiguous allocation (α = 0) decreases the latency and power dissipation of the network and improves the applications execution time. However, it limits the achievable throughput and increases the turnaround time of the applications. As a result, recent works consider non-contiguous allocation (α = 1) to improve the throughput traded off against applications execution time and network metrics. In contradiction, our experiments show that a higher throughput (by 3%) with improved network performance can be achieved when using intermediate α values. More precisely, up to 35% drop in the network costs can be gained by adjusting the level of contiguity compared to non-contiguous cases, while the achieved throughput is kept constant. Moreover, CASqA provides at least 32% energy saving in the network compared to other works.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	349
Ending Page	354
File Size	205369
Page Count	6
File Format	PDF
ISBN	9781479928163
DOI	10.1109/ASPDAC.2014.6742914
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-20
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resource management Throughput Dispersion Measurement Program processors Power dissipation Energy dissipation Contiguous Task Mapping Processor allocation Application Mapping Dynamic Many-Core Systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems

Adjustable Contiguity of Run-Time Task Allocation in Networked Many-Core Systems

CoNA: Dynamic application mapping for congestion reduction in many-core systems

Smart hill climbing for agile dynamic mapping in many-core systems

Multi Rectangle Modeling Approach for Application Mapping on a Many-Core System

Software platform for hybrid resource management of a many-core accelerator for multimedia applications

ARTE: An Application-specific Run-Time management framework for multi-core systems

WeNA: Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems

Pattern-Based Systematic Task Mapping for Many-Core Processors

Adjustable contiguity of run-time task allocation in networked many-core systems

Similar Documents

Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems

Adjustable Contiguity of Run-Time Task Allocation in Networked Many-Core Systems

CoNA: Dynamic application mapping for congestion reduction in many-core systems

Smart hill climbing for agile dynamic mapping in many-core systems

Multi Rectangle Modeling Approach for Application Mapping on a Many-Core System

Software platform for hybrid resource management of a many-core accelerator for multimedia applications

ARTE: An Application-specific Run-Time management framework for multi-core systems

WeNA: Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems

Pattern-Based Systematic Task Mapping for Many-Core Processors

Adjustable contiguity of run-time task allocation in networked many-core systems