NDLI: Reducing dynamic compilation overhead by overlapping compilation and execution

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Transition-based coverage estimation for symbolic model checking

Word level functional coverage computation

Discovering the input assumptions in specification refinement coverage

Refinement strategies for verification methods based on datapath abstraction

Generation of shorter sequences for high resolution error diagnosis using sequential SAT

Constraint-driven bus matrix synthesis for MPSoC

Improving routing efficiency for network-on-chip through contention-aware input selection

Physical design implementation of segmented buses to reduce communication energy

Co-synthesis of a configurable SoC platform based on a network on chip architecture

Customized SIMD unit synthesis for system on programmable chip - a foundation for HW/SW partitioning with vectorization

Robust analytical gate delay modeling for low voltage circuits

CGTA: current gain-based timing analysis for logic cells

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths

Crosstalk analysis using reconvergence correlation

Process-induced skew reduction in nominal zero-skew clock trees

A low dynamic power and low leakage power 90-nm CMOS square-root circuit

A high-throughput low-power fully parallel 1024-bit 1/2 -rate low density parity check code decoder in 3D integrated circuits

A 16-bit, low-power microsystem with monolithic MEMS-LC clocking

Ultra-low voltage power management circuit and computation methodology for energy harvesting applications

A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression

An implementation of a CMOS down-conversion mixer for GSM1900 receiver

Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors

Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback

A built-in power supply noise probe for digital LSIs

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35/spl mu/m CMOS technology

Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices

High-throughput decoder for low-density parity-check code

Hardware implementation of super minimum all digital FM demodulator

Designing a custom architecture for DCT using NISC technology

A 52mW 1200MIPS compact DSP for multi-core media SoC

Implementation of H.264/AVC decoder for mobile video applications

A high-performance platform-based SoC for information security

Configurable multi-processor architecture and its processor element design

Design and implementation of transducer for ARM-TMS communication

Energy savings through embedded processing on disk system

Energy-aware computation duplication for improving reliability in embedded chip multiprocessors

Object duplication for improving reliability

Mapping and configuration methods for multi-use-case networks on chips

Conversion of reference C code to dataflow model H.264 encoder case study

SAVS: a self-adaptive variable supply-voltage technique for process-tolerant and power-efficient multi-issue superscalar processor design

The design and implementation of a low-latency on-chip network

A near optimal deblocking filter for H.264 advanced video coding

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

Prefetching-aware cache line turnoff for saving leakage energy

A robust detailed placement for mixed-size IC designs

FastPlace 2.0: an efficient analytical placer for mixed-mode designs

Timing-driven placement based on monotone cell ordering constraints

Constraint driven I/O planning and placement for chip-package co-design

Simultaneous block and I/O buffer floorplanning for flip-chip design

Electrothermal analysis and optimization techniques for nanoscale integrated circuits

Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems

Area optimization for leakage reduction and thermal stability in nanometer scale technologies

Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology

An anytime symmetry detection algorithm for ROBDDs

High level equivalence symmetric input identification

Fast multi-domain clock skew scheduling for peak current reduction

Low area pipelined circuits by multi-clock cycle paths and clock scheduling

A transduction-based framework to synthesize RSFQ circuits

Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomena

Newton: a library-based analytical synthesis tool for RF-MEMS resonators

Jitter decomposition in ring oscillators

A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels

Double edge triggered feedback flip-flop in sub 100nm technology

Post-routing redundant via insertion for yield/reliability improvement

Temperature-aware routing in 3D ICs

Closed form solution for optimal buffer sizing using the Weierstrass elliptic function

An O(mn) time algorithm for optimal buffer insertion of nets with m sinks

Spec-based flip-flop and latch repeater planning

Current trends in flash memory technology

Configurability of performance and overheads in flash management

Delay defect screening for a 2.16 GHz SPARC64 microprocessor

A dynamic test compaction procedure for high-quality path delay testing

Delay variation tolerance for domino circuits

Efficient identification of multicycle false path

IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults

High-level architecture exploration for MPEG4 encoder with custom parameters

Programmable numerical function generators based on quadratic approximation: architecture and synthesis method

An automated design flow for 3D microarchitecture evaluation

Optimal topology exploration for application-specific 3D architectures

Task placement heuristics based on 3D-adjacency and look-ahead in reconfigurable systems

A quasi-Newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings

An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits

Optimization of circuit trajectories: an auxiliary network approach

SASIMI: sparsity-aware simulation of interconnect-dominated circuits with nonlinear devices

An unconditional stable general operator splitting method for transistor level transient analysis

An introduction to openaccess an open source data model and API for IC design

OpenAccess overview: industrial experience

EDA vendor adoption

Utility of the OpenAccess database in academic research

Depth-driven verification of simultaneous interfaces

FSM-based transaction-level functional coverage for interface compliance verification

Hardware debugging method based on signal transitions and transactions

Cycle error correction in asynchronous clock modeling for cycle-based simulation

A fast logic simulator using a look up table cascade emulator

Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system

Optimal TDMA time slot and cycle length allocation for hard real-time systems

POSIX modeling in SystemC

PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs

Wire sizing with scattering effect for nanoscale interconnection

Adaptive admittance-based conductor meshing for interconnect analysis

Interconnect RL extraction at a single representative frequency

An efficient algorithm for 3D reluctance extraction considering high frequency effect

Macromodelling oscillators using Krylov-subspace methods

Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems

Single-chip multiprocessor integrating quadruple 8-Way VLIW processors with interface timing analysis considering power supply noise

A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation

PowerViP: SoC power estimation framework at transaction level

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems

Analysis and optimization of gate leakage current of power gating circuits

Delay modeling and static timing analysis for MTCMOS circuits

Switching-activity driven gate sizing and Vth assignment for low power design

Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-Vdd designs

Reusable component IP design using refinement-based design environment

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications

A novel instruction scratchpad memory optimization method based on concomitance metric

DraXRouter: global routing in X-architecture with dynamic resource assignment

Diagonal routing in high performance microprocessor design

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model

A novel framework for multilevel full-chip gridless routing

Monotonic parallel and orthogonal routing for single-layer ball grid array packages

A routability constrained scan chain ordering technique for test power reduction

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability

A memory grouping method for sharing memory BIST logic

Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation

A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles

Parasitics extraction involving 3-D conductors based on multi-layered Green's function

Signal-path driven partition and placement for analog circuit

An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis

Statistical corner conditions of interconnect delay (corner LPE specifications)

Speed binning aware design methodology to improve profit under parameter variations

Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)

A probabilistic analysis of pipelined global interconnect under process variations

Yield-preferred via insertion based on novel geotopological technology

Introduction to H.264 advanced video coding

Algorithms and DSP implementation of H.264/AVC

Hardware architecture design of an H.264/AVC video codec

ASIP approach for implementation of H.264/AVC

Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs

A fixed-die floorplanning algorithm using an analytical approach

A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers

Design Space Exploration for Minimizing Multi-Project Wafer Production Cost

SAT-based optimal hypergraph partitioning with replication

Finding optimal L1 cache configuration for embedded systems

Memory size computation for multimedia processing applications

Maximizing data reuse for minimizing memory space requirements and execution cycles

Compiler-guided data compression for reducing memory consumption of embedded applications

Analysis of scratch-pad and data-cache performance using statistical methods

Efficient early stage resonance estimation techniques for C4 package

Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters

Power distribution techniques for dual VDD circuits

Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method

Controlling inductive cross-talk and power in off-chip buses using CODECs

A new test and characterization scheme for 10+ GHz low jitter wide band PLL

An SPU reference model for simulation, random test generation and verification

A cycle accurate power estimation tool

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

TAPHS: thermal-aware unified physical-level and high-level synthesis

An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model

Abridged addressing: a low power memory addressing strategy

Using speculative computation and parallelizing techniques to improve scheduling of control based designs

Worst case execution time analysis for synthesized hardware

Workload prediction and dynamic voltage scaling for MPEG decoding

Lazy BTB: reduce BTB energy consumption using dynamic profiling

Cache size selection for performance, energy and reliability of time-constrained systems

Reducing dynamic compilation overhead by overlapping compilation and execution

Functional modeling techniques for efficient SW code generation of video codec applications

Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops

Parameterized block-based non-Gaussian statistical gate timing analysis

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

Statistical Bellman-Ford algorithm with an application to retiming

An exact algorithm for the statistical shortest path problem

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Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

Proceedings of 1998 Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

Reducing dynamic compilation overhead by overlapping compilation and execution

Content Provider	IEEE Xplore Digital Library
Author	Unnikrishnan, P. Kandemir, M. Li, E.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Pennsylvania State Univ. (Unnikrishnan, P.; Kandemir, M.; Li, E.)
Abstract	An important problem in executing applications in energy-sensitive embedded environments is to tune their behavior based on dynamic variations in energy constraints. One option for achieving this is dynamic compilation ~ compiling code fragments on the fly to adapt to changing energy demands. While dynamic compilation can be very beneficial in many embedded environments where multiple criteria need to be satisfied during execution, it can also incur a significant performance overhead since compilation takes place at runtime. The goal in this work is to reduce this performance overhead of dynamic compilation by overlapping it with application execution. Specifically, provided that we have available hardware resources to perform dynamic compilation concurrently with application execution, our approach compiles the next code fragment to be executed while we are executing the current code fragment. The experimental results from our implementation indicate significant savings in execution times. Our experimental results also indicate that the proposed strategy performs consistently well under different parameters
File Size	288923
File Format	PDF
ISBN	0780394518
DOI	10.1109/ASPDAC.2006.1594805
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dynamic compiler Batteries Hardware Joining processes Algorithms Computer science Power engineering and energy Application software Runtime environment Optimizing compilers
Content Type	Text
Resource Type	Article

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