NDLI: Simultaneous block and I/O buffer floorplanning for flip-chip design

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Simultaneous block and I/O buffer floorplanning for flip-chip design

Content Provider	IEEE Xplore Digital Library
Author	Chih-Yang Peng Wen-Chang Chao Yao-Wen Chang Jyh-Herng Wang
Copyright Year	2006
Description	Author affiliation: Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei (Chih-Yang Peng; Wen-Chang Chao)
Abstract	The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplanning problem for the flip-chip design and formulate it as assigning the positions of input/output buffers and first-stage/last-stage blocks so that the path length between blocks and bump balls as well as the delay skew of the paths are simultaneously minimized. We then present a hierarchical method to solve the problem. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the alternating and interacting global optimization step and the partitioning step. The global optimization step places blocks based on simulated annealing using the B-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the blocks are divided into two groups and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of blocks, defined by the ratio of the total block area to the chip area. At last, we refine the floorplan by perturbing blocks inside a subregion as well as in different subregions. Compared with the B-tree based floorplanner alone, our method is more efficient and obtains significantly better results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial flip-chip designs provided by leading companies
File Size	313376
File Format	PDF
ISBN	0780394518
DOI	10.1109/ASPDAC.2006.1594684
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Integrated circuit interconnections Design engineering Electronics packaging Application specific integrated circuits Chaos Delay Simulated annealing Cost function Bonding
Content Type	Text
Resource Type	Article

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