NDLI: Controlling inductive cross-talk and power in off-chip buses using CODECs

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Controlling inductive cross-talk and power in off-chip buses using CODECs

Content Provider	IEEE Xplore Digital Library
Author	LaMeres, B.J. Gulati, Kanupriya Khatri, S.P.
Copyright Year	2006
Description	Author affiliation: Design Validation Div., Agilent Technol. Inc., Colorado Springs, CO (LaMeres, B.J.)
Abstract	The parasitic inductances within IC packaging cause supply bounce as well as glitches on the signal pins, significantly limiting the frequency of high-speed inter-chip communication. Also, off-chip communication contributes a large fraction of the total system power. Until recently, the parasitic inductance problem was addressed by aggressive package design, which is expensive. In this work we present a technique to encode the off-chip data transmission to i) limit bounce on the supplies, ii) reduce glitching caused by inductive signal coupling from neighboring signals, iii) limit the edge degradation of signals due to mutually inducted voltages from neighboring switching signals and iv) control the total power consumption of the I/O logic. All these factors are modeled in a unified mathematical framework. Our experimental results show that the proposed encoding based techniques result in reduced supply bounce and signal glitching due to inductive cross-talk, closely matching the theoretical predictions. Also, we show that the bus size overhead is reasonable even after stringent power reduction constraints are imposed. We demonstrate that the overall bandwidth of a bus actually increases by 100% over an unencoded bus, using our technique with inductive constraints only (even after accounting for the encoding overhead). When the power constraints were added (to limit the power to 20% of worst case switching power) in addition to the inductive constraints, the bandwidth was again 100% improved over the unencoded bus. The asymptotic bus size overhead depends on how stringent the user-specified power and inductive cross-talk parameters are. We have validated our approach by simulating it in an ASIC setting as well as prototyping and testing it in an FPGA environment
File Size	1078125
File Format	PDF
ISBN	0780394518
DOI	10.1109/ASPDAC.2006.1594792
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Codecs Encoding Bandwidth Communication system control Integrated circuit packaging Pins Frequency Inductance Data communication Mutual coupling
Content Type	Text
Resource Type	Article

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