NDLI: Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration

Content Provider	IEEE Xplore Digital Library
Author	Bouchhima, A. Bacivarovx, I. Youssef, W. Bonaciu, M. Jerraya, A.A.
Copyright Year	2005
Description	Author affiliation: Syst. Level Synthesis Group, TIMA Lab., Grenoble, France (Bouchhima, A.; Bacivarovx, I.; Youssef, W.; Bonaciu, M.; Jerraya, A.A.)
Abstract	Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC architectures is a key enabler to manage this complexity and thus to enhance design productivity. In this paper, we describe an abstract, high level CPU subsystem model that captures the specificities of such MP-SoC architectures, along with a timed co-simulation environment to perform early exploration of the entire HW/SW design. The model is based on the Hardware Abstraction Layer (HAL) concept allowing the validation of complex applications written on top of real-life operating systems. Experimentation with a MPEG4 application proves the interest of the proposed methodology.
Sponsorship	Chinese Inst. of Electron
Starting Page	969
Ending Page	972
File Size	769837
Page Count	4
File Format	PDF
ISBN	0780387368
DOI	10.1109/ASPDAC.2005.1466501
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Instruction sets Hardware MPEG 4 Standard Computer architecture Wires Laboratories Strontium Costs Productivity
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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