NDLI: Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms

Content Provider	IEEE Xplore Digital Library
Author	Zhe Ma Catthoor, F. Vounckx, J.
Copyright Year	2005
Description	Author affiliation: IMEC/DESICS, Leuven, Belgium (Zhe Ma; Catthoor, F.; Vounckx, J.)
Abstract	Nowadays, the system-on-a-chip (SoC) has integrated more processors onto a single chip. Applications are also consisting of multiple (sub) tasks that are presented as different source code which can be partly executed concurrently. However, the subtask-level parallelism inside a single task is often too limited to fully utilize all the parallel processors and results in many slacks on processors. To better use the processors, subtasks of multiple tasks will have to be executed in an interleaving fashion. This paper proposes design-time algorithms to interleave subtasks based on the separated schedules of tasks. This interleaver can be considered as part of a hierarchical scheduler to steer the code generation of very complex applications with many tasks. The scheduling experiments show that the execution time can be shortened by 20%-30% when interleaving two tasks against the sequential execution without subtask interleaving. Moreover, the differences between the solutions given by our scheduling algorithm and the optimal solutions are less than 6% for up to 20 subtasks.
Sponsorship	Chinese Inst. of Electron
Starting Page	952
Ending Page	955
File Size	680133
Page Count	4
File Format	PDF
ISBN	0780387368
DOI	10.1109/ASPDAC.2005.1466497
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interleaved codes Scheduling algorithm Processor scheduling Clustering algorithms System-on-a-chip Switches Algorithm design and analysis Digital signal processing chips Application specific processors Time to market
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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