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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kahng, A.B. |
| Copyright Year | 2001 |
| Description | Author affiliation: Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA (Kahng, A.B.) |
| Abstract | Future requirements for design technology are always uncertain due to changes in process technology, system implementation platforms, and applications markets. To correctly identify the design technology need, and to deliver this technology at the right time, the design technology community-commercial vendors, captive CAD organizations, and academic researchers-must focus on improving design technology time-to-market and quality-of-result. Put another way, we must address the well-known design productivity gap by addressing the design technology productivity gap. The future of design technology is most uncertain in the physical implementation space, where many complexities must be managed without sacrificing system value or turnaround time. This talk will begin with examples of changes in methodology and design tool infrastructure needed to support future physical implementation. Then, recent initiatives in the MARCO Gigascale Silicon Research Center (GSRC) are described which support the design technology and designer communities in creating the right design technology when it is needed. |
| Sponsorship | IEEE Circuits & Syst. Soc. |
| Starting Page | 443 |
| Ending Page | 448 |
| File Size | 891767 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780366336 |
| DOI | 10.1109/ASPDAC.2001.913348 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-02-02 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Productivity Timing Space technology Costs Wire Time to market Silicon Logic design Design optimization Switches |
| Content Type | Text |
| Resource Type | Article |
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