NDLI: Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks

Content Provider	IEEE Xplore Digital Library
Author	Yan, K.
Copyright Year	2001
Description	Author affiliation: ZettaCom, San Jose, CA, USA (Yan, K.)
Abstract	In some modern FPGAs and CPLDs, PLA (programmable logic array)-style logic blocks can be used as the storage elements for improved logic density and performance. PLA-style logic blocks were originally deployed in the early PLDs. Due to recent research developments in the FPGA community, PLA-style logic blocks are becoming an effective storage alternative in FPGAs. This paper presents an approach with clustering and functional decomposition to implement the circuit using the minimum number of PLA-style logic blocks. One important feature is that it simultaneously considers the routing resource reduction for better circuit performance after place-and-route. In order to effectively use PLA-style logic blocks in large clusters, functional decompositions are used to decompose large clusters so that the encoding functions and base functions can be mapped into PLA-blocks. Furthermore, implicit representation of the crucial steps in the functional decomposition is used to consider: 1) number of inputs; 2) number of product terms; and 3) number of outputs required for the PLA-block synthesis. We have developed an algorithm called PLA-SynT that can be used in the logic synthesis flow for CPLDs and FPGAs with PLA-blocks. MCNC benchmarks are used to test PLA-SynT and the experimental results are compared with TEMPLA. PLA-SynT shows 10.24% improvement over TEMPLA, in terms of the number of PLA-blocks needed to implement the circuit. PLA-SynT also shows 14.41% improvement over EMB-Syn in circuit performances while maintaining comparable circuit areas.
Sponsorship	IEEE Circuits & Syst. Soc.
Starting Page	231
Ending Page	234
File Size	478464
Page Count	4
File Format	PDF
ISBN	0780366336
DOI	10.1109/ASPDAC.2001.913310
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-02-02
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Logic arrays Routing Logic devices Logic circuits Delay Circuit synthesis Table lookup Integrated circuit interconnections Logic functions
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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