NDLI: Estimation of peak current through CMOS VLSI circuit supply lines

Content Provider	IEEE Xplore Digital Library
Author	Murayama, T. Ogawa, K. Yamaguchi, H.
Copyright Year	1999
Description	Author affiliation: Sony Corp., Atsugi, Japan (Murayama, T.)
Abstract	We present a new approach for estimating the maximum instantaneous current through the power supply lines of CMOS VLSI circuits. Our final goal is to determine the peak currents and voltage drops through power supply lines of real VLSI circuits within a practical time. Our approach is based on the iMax algorithm of estimating the upper bound of the current, and uses an improved timed ATPG-based algorithm to obtain a tight lower bound. In order to handle sequential circuits, we equate latch outputs with primary inputs for the upper bound estimation and use a logic simulator to determine the initial values for the lower bound estimation. Based on the information obtained, we model all blocks in the circuit as voltage-controlled current sources, with the analog hardware description language (AHDL). After extracting parasitic resistances of the power supply lines, we simulate the entire circuit using an analog simulator and obtain the maximum current estimation and voltage drops in the supply lines. In the modeling procedure we take the negative feedback influence into consideration such that the estimated current reflects a real switching transition. We have implemented the theoretically modeled negative feedback influence into our simulator called PANGI. Some experimental results of applying PANGI to the circuits which consist of more than 1M gates prove the accuracy and reliability of our approach.
Starting Page	295
Ending Page	298
File Size	413745
Page Count	4
File Format	PDF
ISBN	078035012X
DOI	10.1109/ASPDAC.1999.760017
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-01-21
Publisher Place	Hong Kong
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Circuit simulation Power supplies Voltage Upper bound Sequential circuits Negative feedback Latches Hardware design languages Data mining
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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