NDLI: Pin assignment and routing on a single-layer pin grid array

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Transistor reordering rules for power reduction in CMOS gates

Power reduction by gate sizing with path-oriented slack calculation

Current and charge estimation in CMOS circuits

Auriga2: a 4.7 million-transistor CISC microprocessor

Automatic design for bit-serial MSPA architecture

Stoht-an SDL-to-Hardware Translator

Enhancing a VHDL based design methodology with application specific data abstraction

A scheduling algorithm for synthesis of bus-partitioned architectures

Reclocking for high level synthesis

Synthesis of false loop free circuits

High-level synthesis scheduling and allocation using genetic algorithms

A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems

Generic fuzzy logic CAD development tool

A hardware/software codesign method for pipelined instruction set processor using adaptive database

EMPAR: an interactive synthesis environment for hardware emulations

A scheduling algorithm for multiport memory minimization in datapath synthesis

An integrated hardware-software cosimulation environment for heterogeneous systems prototyping

A CSIC implementation with POCSAG decoder and microcontroller for paging applications

Performance-driven circuit partitioning for prototyping by using multiple FPGA chips

A new system partitioning method under performance and physical constraints for multi-chip modules

A robust min-cut improvement algorithm based on dynamic look-ahead weighting

Timing influenced general-cell genetic floorplanner

Power analysis of a 32-bit embedded microcontroller

Assessing the feasibility of interface designs before their implementation

A hardware-software co-simulator for embedded system design and debugging

Integrated interconnect circuit modeling for VLSI design

Architectural simulation for a programmable DSP chip set

System-level verification of CDMA modem ASIC

A digital audio signal processor for cellular phone application

Region definition and ordering assignment with the minimization of the number of switchboxes

A three-layer over-the-cell multi-channel routing method for a new cell model

Pin assignment and routing on a single-layer pin grid array

Design for testability using register-transfer level partial scan selection

A built-in self test scheme for VLSI

BIST with negligible aliasing through random cover circuits

Implicit prime compatible generation for minimizing incompletely specified finite state machines

Logic optimization by an improved sequential redundancy addition and removal technique

On hazard-free implementation of speed-independent circuits

Extending pitchmatching algorithms to layouts with multiple grid constraints

A new layout synthesis for leaf cell design

A layout approach to monolithic microwave IC

Performance driven multiple-source bus synthesis using buffer insertion

Communication based FPGA synthesis for multi-output Boolean functions

Optimum PLA folding through boolean satisfiability

Technology mapping for FPGAs with complex block architectures by fuzzy logic technique

Logic rectification and synthesis for engineering change

A new k-way partitioning approach for multiple types of FPGAs

Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs with performance optimization

Routing on regular segmented 2-D FPGAs

Flexible optimization of fixed polarity Reed-Muller expansions for multiple output completely and incompletely specified Boolean functions

GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions

Learning heuristics by genetic algorithms

Optimization methods for lookup-table-based FPGAs using Transduction Method

A new and accurate interconnection delay time evaluation in a general tree-type network

An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation

A model-adaptable MOSFET parameter extraction system

Improved computational methods and lazy evaluation of the Ordered Ternary Decision Diagram

Manipulation of regular expressions under length constraints using zero-suppressed-BDDs

Exploiting signal flow and logic dependency in standard cell placement

A new performance driven placement method with the Elmore delay model for row based VLSIs

A neural network approach to the placement problem

Fanout-tree restructuring algorithm for post-placement timing optimization

Some remarks about spectral transform interpretation of MTBDDs and EVBDDs

Synthesis and simulation of digital demodulator for infrared data communication

A design of high-performance multiplier for digital video transmission

Design automation for integrated continuous-time filters using integrators

A hardware-oriented design for weighted median filters

Techniques for low power realization of FIR filters

EDIF Version 350/400 and information modelling

Delay abstraction in combinational logic circuits

Limits of using signatures for permutation independent Boolean comparison

A tool for measuring quality of test pattern for LSIs' functional design

Search space reduction in high level synthesis by use of an initial circuit

A datapath synthesis system for the reconfigurable datapath architecture

Synthesis-for-testability using transformations

Applying formal verification to a commercial microprocessor

Verifying pipelined microprocessors

Formal verification of pipelined and superscalar processors

Evaluation and composition of specification languages, an industrial point of view

A methodology for the development of integrated and open HDL-based design environments

Performance verification using PDL and constraint satisfaction

Design of a DBMS for VHDL-based CAD environments

Time parameterized function method: a new method for hardware verification with the Boyer-Moore Theorem Prover

Object-oriented co-synthesis of distributed embedded systems

Multi-level equivalence in design transformation

Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits

Description and verification of RTL designs using multiway decision graphs

An intelligent, self-deducing graphical register transfer interface based on a distributed constraint logic computation

The T-Ruby design system

Correctness of transformations in high level synthesis

High level synthesis of asynchronous circuit targeting state machine controllers

A model of VHDL for the analysis, transformation, and optimization of digital system designs

Explicit-enumeration based verification made memory-efficient

Automatic verification of memory systems which service their requests out of order

Symbolic verification of hardware systems

The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor

A prover for VHDL-based hardware design

Complete visual specification and animation of protocols

Transformation of timing diagram specifications into VHDL code

Integrating design and verification environments through a logic supporting hardware diagrams

Extending VHDL for state based specifications

A design and verification environment for ELLA

HML: an innovative hardware description language and its translation to VHDL

Silicon single-electron transistors on a SIMOX substrate

Test pattern embedding in sequential circuits through cellular automata

Efficiency comparison of signature monitoring schemes for FSMs

A state encoding for self-checking finite state machines

Algebraic error detection: a new approach to concurrent error detection in arithmetic circuits

Fast generalized arithmetic and adding transforms

An evolution-based technique for local microcode compaction

Optimum simultaneous placement and binding for bit-slice architectures

Critical view on the current sensor application for self-timing in VLSI systems

Design and verification of a self-timed RAM

A profile driven approach for low power synthesis

Low power and very low EMI, high efficiency, high frequency crystal oscillator

A mathematically sound approach to the correct design of hardware

C++ base classes for specification, simulation and partitioning of a hardware/software system

Fast prototyping for telecom components using a synthesizeable VHDL flexible library

An efficient design environment and algorithms for transport processing FPGA

Finding best cones from random clusters for FPGA package partitioning

On variable ordering and decomposition type choice in OKFDDs

Implementation of a recursive real time edge detector using retiming techniques

Graceful capacity degradation for ultra-large hierarchical memory structures

Cellular automata-based collision-free robot path planning

A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy

Wire routing by Lagrangian method

A Full Over-the-Cell routing model

Routing space estimation and safe assignment for macro cell placement

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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