NDLI: Auriga2: a 4.7 million-transistor CISC microprocessor

Content Provider	IEEE Xplore Digital Library
Author	Tual, J.P. Thill, M. Bernard, C. Nguyen, H.N. Mottini, F. Moreau, M. Vallet, P.
Copyright Year	1995
Description	Author affiliation: Bull SA, Les Clayes-sous-Bois, France (Tual, J.P.; Thill, M.; Bernard, C.; Nguyen, H.N.; Mottini, F.; Moreau, M.; Vallet, P.)
Abstract	With the introduction of the high range version of the DPS7000 mainframe family, Bull is providing a processor which integrates the DPS7000 CPU and first level of cache on one VLSI chip containing 4.7M transistors and using a 0.5 pm, 3Mlayers CMOS technology. This enhanced CPU has been designed to provide a high integration, high performance and low cost systems. Up to 24 such processors can be integrated in a single system, enabling performance levels in the range of 850 TPC-A (Oracle) with about 12 000 simultaneously active connections. The design methodology involved massive use of formal verification and symbolic layout techniques, enabling to reach first pass right silicon on several foundries. An architectural overview of the CPU with emphasis on several original aspects of the design aspects (synthesis, verification, symbolic layout) are discussed in this paper.
Starting Page	19
Ending Page	25
File Size	741755
Page Count	7
File Format	PDF
ISBN	4930813670
DOI	10.1109/ASPDAC.1995.486196
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-08-29
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Central Processing Unit CMOS technology Circuits Hardware CMOS process Out of order Formal verification Foundries Random access memory
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Auriga2: a 4.7 million-transistor CISC microprocessor

Auriga2, a 4,7 Million Transistor CISC Processor for a High-End Mainframe

Microprocessor Technology For Psychiatrists

Performance features of the PA7100 microprocessor

A 4-transistor static memory cell design with a standard CMOS process

A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interface

A fail-safe microprocessor using dual synthesizable processor cores

Formal verification of microprocessors

Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

Auriga2: a 4.7 million-transistor CISC microprocessor

Similar Documents

Auriga2: a 4.7 million-transistor CISC microprocessor

Auriga2, a 4,7 Million Transistor CISC Processor for a High-End Mainframe

Microprocessor Technology For Psychiatrists

Performance features of the PA7100 microprocessor

A 4-transistor static memory cell design with a standard CMOS process

A 32-bit superscalar microprocessor with 64-bit processing and high bandwidth DRAM interface

A fail-safe microprocessor using dual synthesizable processor cores

Formal verification of microprocessors

Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

Auriga2: a 4.7 million-transistor CISC microprocessor