NDLI: Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Bernardeschi, C. Cassano, L. Domenici, A. Sterpone, L.
Copyright Year	2012
Description	Author affiliation: Dipartimento di Automatica ed Informatica, Politecnico di Torino, Italy (Sterpone, L.) \|\| Department of Information Engineering, University of Pisa, Italy (Bernardeschi, C.; Cassano, L.; Domenici, A.)
Abstract	SRAM-based FPGAs are more and more relevant in a growing number of applications, ranging from the automotive to the aerospace ones. Designers of safety-critical applications demand accurate methodologies to evaluate the Single Event Upsets (SEUs) sensitivity of their designs. In this paper, we present an accurate simulation method for the evaluation of the effects of SEUs in the configuration memory of SRAM-based FPGAs. The approach is able to simulate SEUs affecting the configuration memory of both logic and routing resources since it is able to accurately model the electrical behavior of SEUs in the configuration memory. Detailed experimental results on a large set of benchmark circuits are provided and the comparison with fault injection experiments is shown in order to validate the accuracy of the proposed method. The results clearly demonstrate the benefits of our approach since simulation results predict almost completely the results obtained through fault injection.
Starting Page	115
Ending Page	120
File Size	323754
Page Count	6
File Format	PDF
ISBN	9781467330435
e-ISBN	9781467330442
DOI	10.1109/DFT.2012.6378210
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Field programmable gate arrays Routing Analytical models Integrated circuit modeling Table lookup Switches static analysis Single Event Upsets SRAM-based FPGAs fault simulation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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