NDLI: Built-in self-reconfiguring systems for mesh-connected processor arrays with spares on two rows/columns

Content Provider	IEEE Xplore Digital Library
Author	Takanami, I.
Copyright Year	2000
Description	Author affiliation: Ichinoseki Nat. Coll. of Technol., Iwate, Japan (Takanami, I.)
Abstract	The author discusses some reconfiguration methods where faulty PEs are compensated for by spare PEs located in two rows/columns in/around a mesh-connected array since they have the advantages that the numbers of spare PEs and the network overheads for reconstructions are relatively small. First, the author discusses how arrangements of spare PEs and network architectures affect the efficiencies of reconfigurations. As arrangements of spare PEs, he considers the cases where either spare linear arrays face each other or are located orthogonally. As replacements of faulty PEs by spare PEs, straight shifts using double or single tracks are considered. Reconfiguration algorithms are given for the proposed methods. The efficiencies of reconfigurations for the methods, that is, the reconfiguration probabilities, are compared with each other. Finally, the author presents built-in self-reconfiguring systems for the proposed methods by hardware. This implies that the proposed methods are effective in enhancing the run-time reliabilities as well as the fabrication-time yields of the processor arrays.
Starting Page	213
Ending Page	221
File Size	392730
Page Count	9
File Format	PDF
ISBN	0769507190
ISSN	10636722
DOI	10.1109/DFTVS.2000.887159
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Concurrent computing Hardware Runtime Educational institutions Image reconstruction Signal processing Image processing Very large scale integration Wafer scale integration
Content Type	Text
Resource Type	Article

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