NDLI: Systolic architectures based on barrel shifters for real-time signal and image processing

Content Provider	IEEE Xplore Digital Library
Author	Ramamoorthy, P. Tau Chen
Copyright Year	1985
Description	Author affiliation: University of Cincinnati, Cincinnati, OH (Ramamoorthy, P.)
Abstract	The throughput in real-time digital signal processing (DSP) applications is limited by both the capability of the processors employed for number-crunching operations and the capacity of a supporting communications link. The systolic architectures eliminate the memory bandwidth problems by allowing multiple computations for each memory access and hence makes possible a high throughput in real-time applications. In conventional systolic arrays, the computational element includes a multiplier and an accumulator (MAC). The multiplier in the basic cell requires either large chip area if high speed is desired or time consuming if serial architecture is used. The replacement of the multiplier by the barrel shifter has been proposed in this paper. The new basic cell consists of a barrel shifter and an accumulator (BSAC). By the variations of the connection among the basic cells, the throughput data rate can be increased significantly. Also, a large reduction in the number of the gates can be achieved. The results obtained indicate that the BSAC-based systolic arrays can outperform the conventional ones and achieve throughput data rate of the order of 100 MHz or higher.
Starting Page	1009
Ending Page	1012
File Size	83233
Page Count	4
File Format	PDF
DOI	10.1109/ICASSP.1985.1168236
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-04-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing Image processing Computer architecture Throughput Systolic arrays Bandwidth Data flow computing Digital signal processing Very large scale integration Equations
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Static-Reconfigurable Systolic Architecture using Barrel Shifters for High Speed Digital Signal Processing

High speed implementation of matrix inversion algorithms in orthogonal systolic architectures

New VLSI systolic array design for real-time digital signal processing

VLSI architectures for block matching algorithms

Modular VLSI architectures for real-time vector quantization

An efficient new systolic architecture for the solution of discrete Fourier transform

High speed architectures for two-dimensional state-space recursive filtering

Optimization of real-time VLSI architectures for distributed arithmetic-based algorithms: application to HDTV filters

Mapping system level functions on to bit level systolic arrays

Systolic architectures based on barrel shifters for real-time signal and image processing

Similar Documents

A Static-Reconfigurable Systolic Architecture using Barrel Shifters for High Speed Digital Signal Processing

High speed implementation of matrix inversion algorithms in orthogonal systolic architectures

New VLSI systolic array design for real-time digital signal processing

VLSI architectures for block matching algorithms

Modular VLSI architectures for real-time vector quantization

An efficient new systolic architecture for the solution of discrete Fourier transform

High speed architectures for two-dimensional state-space recursive filtering

Optimization of real-time VLSI architectures for distributed arithmetic-based algorithms: application to HDTV filters

Mapping system level functions on to bit level systolic arrays

Systolic architectures based on barrel shifters for real-time signal and image processing