NDLI: Structural considerations for large FFT programs on the TI TMS 32010 DSP microchip

Content Provider	IEEE Xplore Digital Library
Author	Morris, L.
Copyright Year	1985
Description	Author affiliation: DSPS Digital Signal Processing Software, Inc., Ottawa, Canada (Morris, L.)
Abstract	The very first analyses of software FFT implementation details ignored such practicalities as amount of main memory available. However, Singleton's classic paper [1] -- appearing at a relatively early date -- described how very large FFT's could be implemented when a limited amount of fast, main data memory (i.e., "core") was available together with a large, but slower, secondary memory (e.g., tapes or discs). In this paper we describe the analogous steps taken in creating a family of time-efficient 64-, 128- and 256-point complex FFT's for the TI TMS 320, a DSP microchip with only 144 words of fast data memory but able to transfer data to and from a 4K program memory at a comparatively slow rate. The objective was to produce the fastest possible FFT's concommitant with having enough of the 4K of program memory remaining to double buffer incoming data and to contain the necessary non-time-critical, compact compact control code required to implement non-trivial DFT-based systems, such as vocoders. The resultant programs have 64/128/256 complex point execution times of 0.535, 2.3, and 6.3 msec, respectively, including bit reversal. This suggests that, for the first time, single chip DFT vocoders are feasible.
Starting Page	1648
Ending Page	1651
File Size	132007
Page Count	4
File Format	PDF
DOI	10.1109/ICASSP.1985.1168205
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-04-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Vocoders Digital signal processing chips Discrete Fourier transforms Kernel Systems engineering and theory Signal analysis Control systems Filters Autocorrelation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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