NDLI: Control Policies for Scheduling of Semiconductor Manufacturing Plants

Content Provider	IEEE Xplore Digital Library
Author	Lu, Steve C. H. Kumar, P. R.
Copyright Year	1992
Description	Author affiliation: Dept. of Electrical and Computer Engineering and Coordinated Science Laboratory, University of Illinois, Urbana, IL 61801 (Lu, Steve C. H.; Kumar, P. R.)
Abstract	Two important goals in scheduling semiconductor manufacturing plants are to minimize the mean and variance of the manufacturing cycle time. The manufacturing cycle time is the time taken by a job to traverse through the manufacturing system and become a finished product. In addition to the obvious economic and competetive adavantages, reducing the cycle time is also beneficial in minimizing the time that a wafer is exposed to contamination during the manufacturing process, thus providing higher yield. On the other hand, a small variance of the cycle time allows tighter production planning, and more consistent on-time deliveries of the end product. To meet these two goals, good input release policies and job scheduling policies have to be determined. The former determines job release control at the system input, while the latter allows proper job sequencing at each processing station. In a recent paper, Wein [3] has reported on the comparative performance of a number of release and scheduling policies on a simulated research and development fabrication line. In this paper, besides the policies studied by Wein, we propose two new scheduling policies, the Least Slack (LS) and the Least Optimized Slack (LOS) policies, and report on their performance in a discrete event simulation. Our preliminary results appear to demonstrate that the LOS scheduling policy can reduce both the mean and standard deviation of cycle times by perhaps significant amounts, especially under heavy traffic.
Starting Page	828
Ending Page	829
File Size	268243
Page Count	2
File Format	PDF
ISBN	0780302109
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-06-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	American Automatic Control Council(AACC)
Subject Keyword	Job shop scheduling Semiconductor device manufacture Manufacturing systems Contamination Manufacturing processes Production planning Control systems Research and development Fabrication Discrete event simulation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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