NDLI: A specialized programming language for coordinating software execution timing in embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Koets, M.A. Lecocke, M.B.
Copyright Year	2014
Description	Author affiliation: Southwest Res. Inst., San Antonio, TX, USA (Koets, M.A.; Lecocke, M.B.)
Abstract	We have developed Representation and Implementation of Temporal Event Sequences (RITES), a domain specific programming language which enables users to precisely specify how software and firmware execute with respect to real time on embedded systems hardware. Precise timing of software and firmware operations is critical to many functions within a space system, including coordination of hardware components, scheduling of spacecraft resources, and execution of communications protocols. RITES provides a highly expressive and precise mechanism to specify when software and firmware operations occur. The programming languages commonly used to develop the software and firmware for space systems (i.e. C, C++, and Verilog) do not have a built-in semantic concept of time. In contrast, RITES allows the specification of scheduled behaviors to be made and modified using concepts natural to the scheduling problem and with a compact, intuitive syntax. RITES components coordinate the activities and temporal behavior of other modules within the system rather than encapsulating complete system behavior. The RITES language is supported by a family of code generators that produce executable implementations of RITES programs. Code generators translate RITES programs to C functions for execution as software on sequential processors and to Verilog hardware description language (HDL) modules for execution within Field Programmable Gate Arrays (FPGAs). Additional code generators produce HDL implementations with error tolerance features allowing execution on FPGAs susceptible to single event effects (SEEs) in environments with significant radiation. Specifically, RITES modules may be automatically implemented as Verilog with local or distributed triple modular redundancy (TMR). We provide several examples of the implementation of precision timed behavior at various timing granularities, including clock-by-clock control of a digital signal processing (DSP) core within an FPGA for efficient execution of signal processing applications, implementation of a time division multiple access (TDMA) radio communications protocol, and a detailed study of the configuration and control of an external image compression ASIC.
Sponsorship	IEEE Aerosp. Electron. Syst. Soc.
Starting Page	1
Ending Page	15
File Size	629771
Page Count	15
File Format	PDF
e-ISBN	9781479916221
DOI	10.1109/AERO.2014.6836258
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Ports (Computers) Software Hardware design languages Microprogramming Field programmable gate arrays Pipelines
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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