NDLI: Highly parallel and fast implementation of stereo vision algorithms on MIMD many-core Tilera architecture

Content Provider	IEEE Xplore Digital Library
Author	Safari, S. Fijany, A. Diotalevi, F. Hosseini, F.
Copyright Year	2012
Description	Author affiliation: School of Electrical and Computer Engineering, University of Tehran, Iran (Safari, S.) \|\| Italian Institute of Technology, Via Morego 30, 16163, Genova, Italy (Fijany, A.; Diotalevi, F.; Hosseini, F.)
Abstract	In this paper we present a fast, and for some cases faster than real-time, implementation of a class of dense stereo vision algorithms including the sum of squared differences (SSD), SSD with left-right check, and SSD with multiple windows, on a low-power MIMD many-core architecture, Tilera. Stereo vision — a method to extract spatial depth information of a scene from two pairs of stereo images — is performed as a primary task and first step in many computer vision applications, e.g. 3D modeling and obstacle detection/avoidance in autonomous vehicles. To reduce the scene conditions in real environment and achieve a robust error rejection, intensive computation for implementing a multiple window with left-right checking scheme is required. Therefore, real-time implementation of these algorithms is a challenging problem, particularly in an embedded application. To the best of our knowledge, our results present the first implementation of any stereo vision algorithm on new emerging MIMD many-core architectures. We have achieved a faster than real-time performance of 207, 118, and 30.45 frames per second for VGA (640×480) images with a disparity range of 16 for standard SSD, SSD with left-right checking, and SSD with 5 multiple window implementations, respectively. For HDTV (1280×720) images, we have achieved rather unique results of 71, and 35.75 frames per second for standard SSD and SSD with left-right checking implementations, respectively. Such excellent performance along with the low power consumption of the Tilera architecture (less than 23W) makes it an excellent candidate to achieve a supercomputing level capability for mobile computer vision applications. Experimental results also clearly demonstrate that the new many-core MIMD parallel architectures can indeed achieve excellent performance in low-level image processing computations while providing a high degree of flexibility and programmability.
Starting Page	1
Ending Page	11
File Size	754286
Page Count	11
File Format	PDF
ISBN	9781457705564
ISSN	1095323X
e-ISBN	9781457705571
DOI	10.1109/AERO.2012.6187228
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Stereo vision Algorithm design and analysis Tiles Real time systems Computational efficiency Engines
Content Type	Text
Resource Type	Article
Subject	Aerospace Engineering Space and Planetary Science

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A cooperative search algorithm for highly parallel implementation of RANSAC for model estimation on Tilera MIMD architecture

Very low power parallel implementation of stereo vision algorithm on a solar cell powered MIMD many core architecture

Wavefront/Systolic Algorithms for Implementation of Stereo Vision and Obstacle Avoidance Computations on a Very Low Power MIMD Many-Core Parallel Architecture: Applications for Mobile Systems and Wearable Visual Guidance"

Fast implementation of dense stereo vision algorithms on a highly parallel SIMD architecture

Implementation of a Stereo Matching algorithm onto a Manycore Embedded System

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1 High Performance Stereo Vision Designed for Massively Data Parallel Platforms

Towards High-Speed Real-Time HTTP Traffic Analysis on the Tilera Many-Core Platform

Post-processing algorithms for real-time active stereo vision

Scaling graph community detection on the Tilera many-core architecture

Highly parallel and fast implementation of stereo vision algorithms on MIMD many-core Tilera architecture

Similar Documents

A cooperative search algorithm for highly parallel implementation of RANSAC for model estimation on Tilera MIMD architecture

Very low power parallel implementation of stereo vision algorithm on a solar cell powered MIMD many core architecture

Wavefront/Systolic Algorithms for Implementation of Stereo Vision and Obstacle Avoidance Computations on a Very Low Power MIMD Many-Core Parallel Architecture: Applications for Mobile Systems and Wearable Visual Guidance"

Fast implementation of dense stereo vision algorithms on a highly parallel SIMD architecture

Implementation of a Stereo Matching algorithm onto a Manycore Embedded System

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1 High Performance Stereo Vision Designed for Massively Data Parallel Platforms

Towards High-Speed Real-Time HTTP Traffic Analysis on the Tilera Many-Core Platform

Post-processing algorithms for real-time active stereo vision

Scaling graph community detection on the Tilera many-core architecture

Highly parallel and fast implementation of stereo vision algorithms on MIMD many-core Tilera architecture